MOS Transistor Via Segmentation for Leakage Reduction
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Solution Overview
Problem
The integration degree of semiconductor devices is limited by the size of conductive vias in MOS transistors, leading to increased parasitic capacitance and leakage current due to the shared via structure between the drain region and the high-K metal gate structure.
Innovation Solution
A method for fabricating MOS transistors that involves forming a semiconductor substrate with shallow trench isolation, a high-K metal gate structure, and conductive vias, where the first conductive via connects both the high-K metal gate and the drain region, and the second conductive via connects the source region, optimizing the structure to reduce the total width of the drain and high-K metal gate structures, thereby minimizing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a shared via structure is used to connect the drain region and high-K metal gate structure, then the total width of the drain and high-K metal gate structures is reduced, but leakage current increases due to the via penetrating into the semiconductor substrate
Solution Approach 1:
The patent divides the semiconductor device into distinct regions with separate conductive vias: a first conductive via connects the drain region to the interlayer dielectric layer without penetrating the semiconductor substrate, while a second conductive via connects the high-K metal gate structure to the interlayer dielectric layer. This segmentation prevents the formation of a continuous conductive path through the substrate that would cause leakage current, while still achieving size reduction through shared interlayer dielectric structures.
Solution Approach 2:
The patent extracts the problematic feature (via penetration into the semiconductor substrate) from the shared via structure. By preventing the first conductive via from penetrating the substrate and instead terminating it at the interlayer dielectric layer, the design eliminates the leakage path while maintaining the benefits of reduced overall device width through shared interconnection structures.
2Productivity
If the size of conductive vias is decreased to increase integration degree, then more devices can be integrated, but the parasitic capacitance of the gate increases and device speed decreases
Solution Approach 1:
The patent applies different structural configurations to different regions of the semiconductor device. The drain region uses a non-penetrating conductive via structure, while the high-K metal gate structure uses a separate conductive via. This local differentiation allows for optimized parasitic capacitance control in the gate region while maintaining compact overall device dimensions, thereby supporting both high integration and high speed performance.
3Area of stationary object
If the size of source regions, drain regions, and high-K metal gate structures is decreased, then integration degree increases, but the conductive via size becomes difficult to decrease further due to process limitations
Solution Approach 1:
The patent transitions from a vertical via penetration approach to a lateral connection approach. Instead of decreasing via size in the vertical dimension (which is limited by process capabilities), the design achieves size reduction by optimizing the lateral dimensions of the conductive vias and their positioning within the interlayer dielectric layer. This dimensional shift allows continued scaling without being constrained by vertical via formation process limits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device integration by reducing the total width of the drain and high-K metal gate structures, thereby decreasing leakage current and allowing for further miniaturization of semiconductor devices.
Implementation Method 1
the metal oxide layer on the top of the metal gate 22 may be removed by an argon sputter process
Data Source
AI summary
A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate; forming a metal gate structure; and forming a source region and a drain region. The method also includes forming a contact-etch-stop layer; forming an interlayer dielectric layer on the contact-etch-stop layer and the metal gate structure; and forming a first opening in the interlayer dielectric layer with a portion of the sidewall spacer and the contact-etch-stop layer left on the bottom. Further, forming a first contact hole in the interlayer dielectric layer by removing the portion of the sidewall spacer and the contact-etch-stop layer. Further, the method also includes forming a first conductive via in the first contact hole.