MOS Transistor Well Isolation for Plasma Charging Compensation
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Solution Overview
Problem
The influence of plasma charging during the manufacturing of semiconductor integrated circuit devices affects both the gate electrode and channel region of MOS-type transistors, leading to characteristic differences and decreased current ratio accuracy in current mirror circuits, particularly because the existing techniques only consider the gate electrode and not the channel region, and are ineffective before the formation of the metal wiring layer.
Innovation Solution
A semiconductor integrated circuit device with a current mirror circuit where both the well of the MOS-type transistor generating the bias and the well receiving the bias are formed insulated and separated from the semiconductor substrate, with a connection circuit that electrically short-circuits the gate electrode and well during manufacturing and disconnects them during mounting, using a first wiring layer to equalize the plasma charging influence on both.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diodes are connected from ground node and power supply node to metal wirings to release charges on gate electrodes, then gate electrode charging influence is reduced, but channel region charging influence remains unaddressed and NMOS transistors cannot be operated
Solution Approach 1:
A potential equalization wiring is introduced as an intermediary element that connects between the gate electrode and the channel region (via the well). This intermediary structure allows the charging influences on both the gate electrode and channel region to be equalized simultaneously, resolving the limitation of previous techniques that could only address gate electrode charging or were incompatible with NMOS transistors
Solution Approach 2:
The invention applies equipotentiality by making the gate electrode and channel region have equal potential through the potential equalization wiring. By connecting these two regions that were previously at different potentials, the voltage difference caused by plasma charging is eliminated, thereby equalizing the electrical characteristics and improving current ratio accuracy
2Reliability
If metal wiring layer is formed first with diodes for charge release, then gate electrode charging is compensated, but plasma charging before metal wiring formation cannot be addressed
Solution Approach 1:
The potential equalization wiring is formed in an earlier stage before the metal wiring layer is deposited. This preliminary formation allows the structure to be in place to handle plasma charging influences that occur during insulating film deposition and contact formation processes, before the metal wiring layer would normally be formed
Solution Approach 2:
The invention adds a new structural dimension by forming the potential equalization wiring beneath the insulating film layer, creating a multi-layer configuration. This allows the equalization function to operate independently of the metal wiring layer formation timing, enabling compensation for plasma charging that occurs at any stage before final device operation
3Ease of manufacture
If channel regions are insulated and separated from semiconductor substrate, then transistor isolation is achieved, but plasma charging on channel regions causes potential differences and characteristic variations
Solution Approach 1:
The invention merges the gate electrode and channel region into an electrically integrated structure through the potential equalization wiring. By connecting these previously separate elements, the charging influences on both components are equalized simultaneously, improving electrical characteristic consistency while maintaining the physical isolation benefits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves high current ratio accuracy by eliminating the influence of plasma charging on both the gate electrode and channel region, ensuring consistent voltage and reducing electrical characteristic changes in MOS-type transistors.
Implementation Method 1
an electrical characteristic such as a threshold voltage or a gain (gm) of the MOS-type transistor is changed by a plasma charging stress of a wiring layer when dry etching for forming the wiring layer or insulating film deposition is performed
Data Source
AI summary
A semiconductor device obtains high current ratio accuracy by eliminating an influence of plasma charging using a MOS-type transistor in which a channel region is isolated and separated from a semiconductor substrate. In a current mirror circuit in which both of a well of a NMOS-type transistor that generates a bias and a well of a NMOS-type transistor that receives the bias are formed insulated and separated from a semiconductor substrate, a connection circuit is connected between gate electrodes and wells of NMOS-type transistors without through the semiconductor substrate, and the connection circuit makes the gate electrodes and the wells in an electrically short-circuited state during manufacturing of the current mirror circuit, and makes the gate electrodes and the wells in a disconnected state in at least one direction during a mounting operation.