MOS Trap Pre-Bias Control for Flicker and RTS Noise

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Solution Overview

Problem

Semiconductor MOS devices suffer from random telegraph signalling (RTS) noise due to traps in the semiconductor material, which is exacerbated by smaller gate areas and smaller process node geometries, affecting noise performance and signal quality, especially in analogue or mixed-signal circuitry.

Innovation Solution

A circuit comprising a MOS device and a bias controller that applies a pre-bias to set the occupancy state of charge carrier traps, reducing noise by selectively varying parameters such as bias voltage, duration, and waveform based on operating conditions like temperature and noise levels, to mitigate RTS noise during operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If smaller process node geometries are used to increase device integration density, then productivity is improved, but RTS noise increases due to greater stresses and defects

Engineering Contradiction:
Improvedevice integration densityVSAvoidRTS noise
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent applies a pre-bias voltage to the MOS device before its normal operation to proactively fill traps with charge carriers and establish a stable occupancy state. This preliminary action prevents traps from randomly capturing and releasing charge carriers during operation, thereby reducing RTS noise while allowing the use of smaller process nodes for higher integration density

Inventive Principle:
Principle #10Preliminary action

2Productivity

If gate area is reduced to increase integration density, then productivity is improved, but RTS noise increases due to proportionally greater impact of trapped charge

Engineering Contradiction:
Improveintegration densityVSAvoidRTS noise
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

By applying a pre-bias voltage before the MOS device enters its active state, the patent ensures that traps are filled with charge carriers in advance. This preliminary conditioning reduces the impact of trapped charge on the channel during operation, enabling the use of smaller gate areas for higher integration density without suffering from increased RTS noise

Inventive Principle:
Principle #10Preliminary action

3Object-generated harmful factors

If pre-bias is applied continuously to reduce RTS noise, then noise performance is improved, but power consumption increases

Engineering Contradiction:
ImproveRTS noiseVSAvoidpower consumption
Core Design Contradiction:
Object-generated harmful factorsVSUse of energy by moving object

Solution Approach 1:

The patent applies the pre-bias voltage periodically or intermittently rather than continuously. The bias controller monitors operating conditions and applies pre-bias only when needed (e.g., before active states or when noise thresholds are exceeded), allowing traps to stabilize without constant power consumption, thus reducing energy usage while maintaining noise performance

Inventive Principle:
Principle #19Periodic action

4Object-generated harmful factors

If high pre-bias voltage is applied to fill traps effectively, then noise performance is improved, but semiconductor material degradesprematurely

Engineering Contradiction:
ImproveRTS noiseVSAvoidsemiconductor material longevity
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The patent dynamically adjusts the pre-bias voltage magnitude based on operating conditions such as temperature, noise thresholds, and device state. Rather than applying a fixed high voltage, the bias controller modulates the pre-bias level to be sufficient for trap filling while minimizing stress on the semiconductor material, thereby reducing degradation and extending device longevity

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11831311B2Control of semiconductor devices
Publication Date: 2023.11.28 CIRRUS LOGIC INC
  • US11831311B2 patent drawing
  • US11831311B2 patent drawing
  • US11831311B2 patent drawing

AI summary

This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (PRO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (PRST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (VPB1, VPB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.