MOS Varactor Island Gates Reduce Series Resistance

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Solution Overview

Problem

MOS varactors with a multi-finger structure suffer from high series resistance and low Q-factor, degrading the performance of LC tanks and voltage-controlled oscillators in millimeter-wave frequency bands.

Innovation Solution

A MOS varactor design featuring island-like gates in a well region of a substrate with direct gate contacts and a specific metal wire configuration, including polysilicon or metal gate electrodes, copper metal wires, and insulating layers to reduce series resistance and enhance the Q-factor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a multi-finger structure is used for MOS varactor, then compatibility with CMOS device structure is improved, but series resistance increases and Q-factor decreases

Engineering Contradiction:
Improvecompatibility with CMOS device structureVSAvoidQ-factor
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The gate electrode is divided into multiple island-like gates arranged in a matrix pattern, which segments the continuous gate structure into discrete units. This segmentation reduces the parasitic resistance by providing multiple parallel conduction paths while maintaining CMOS compatibility through standard fabrication processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate electrodes are arranged in a two-dimensional matrix pattern rather than a one-dimensional multi-finger structure. This dimensional change from linear interdigitated fingers to a grid-like matrix provides additional current paths and reduces series resistance while maintaining the same footprint area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If multi-finger structure is used for MOS varactor, then manufacturing simplicity is improved, but series resistance increases

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidseries resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The gate electrode is segmented into multiple island-like gates arranged in a matrix, creating multiple parallel conduction paths that reduce parasitic resistance. This segmentation is achieved through standard photolithography and etching processes, maintaining manufacturing simplicity while improving electrical performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple island-like gates are merged into a single functional unit through electrical connection via contacts to the doping region. This merging creates a combined low-resistance path while maintaining the segmented structure's benefits for reducing parasitic effects.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If conventional MOS varactor structure is used, then device integration is improved, but Q-factor decreases at millimeter wave frequencies

Engineering Contradiction:
Improvedevice integrationVSAvoidQ-factor
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The transition from one-dimensional multi-finger gates to a two-dimensional matrix array of island-like gates provides additional current paths without increasing device footprint. This dimensional change reduces series resistance and improves Q-factor at millimeter wave frequencies while maintaining high integration density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The doping region is specifically configured with a shape and area that optimizes the local electrical characteristics under and around the island-like gates. This local optimization of the doping region enhances the varactor performance and Q-factor by improving carrier distribution and reducing series resistance in critical areas.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS7989868B2MOS varactor and fabricating method of the same
Publication Date: 2011.08.02 KOREA UNIV IND & ACADEMIC CALLABORATION FOUND
  • US7989868B2 patent drawing
  • US7989868B2 patent drawing
  • US7989868B2 patent drawing

AI summary

A MOS varactor for use in circuits and elements of a millimeter-wave frequency band, which is capable of reducing series resistance and enhancing a Q-factor by using a plurality of island-like gates seated in a well region of a substrate and gate contacts directly over the gates, includes: gate insulating layers arranged at equal intervals in the form of a (n×m) matrix, and a gate electrode placed on the gate insulating layers in a well region of a substrate; a gate contact which contacts the gate electrode; a first metal wire, which is electrically connected to the gate contact; source/drain contacts arranged at equal intervals in a matrix to form apexes of a square centered at the gate electrode and contact a doping region except for the bottom of the gate insulating layers; and a second metal wire, which is electrically connected to the source/drain contacts.