High-Voltage MOS Structure With Vertical Isolation for Breakdown Voltage
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Solution Overview
Problem
Existing high voltage semiconductor devices face challenges in increasing breakdown voltage without enlarging device size or increasing manufacturing costs, particularly in MOS transistors used for 3D NAND flash applications where higher erasing voltages are required.
Innovation Solution
The introduction of additional drift regions and isolation structures in the semiconductor substrate, with specific layouts and doping concentrations, enhances breakdown voltage without increasing the device size by modifying the current path and electric field distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar high-voltage MOS transistor with extended drain is used, then breakdown voltage is increased, but device area is enlarged
Solution Approach 1:
The patent transitions from planar 2D drain structures to vertically extended 3D drain structures that penetrate through the drift region. This dimensional change allows the electric field to be distributed in the vertical direction rather than requiring lateral extension, thereby increasing breakdown voltage without enlarging the top-view device area.
Solution Approach 2:
The drain structure is nested within the drift region, with the drain forming vertical columns that extend through the drift region thickness. This nested configuration allows the drain to be embedded within the drift region volume rather than occupying lateral space, achieving high breakdown voltage with compact footprint.
2Reliability
If lateral diffusion MOS with isolation structure in drain is used, then breakdown voltage at drain is increased, but device area is enlarged
Solution Approach 1:
Instead of using lateral isolation structures that extend in the planar direction, the patent employs vertical isolation through the drift region thickness. The isolation effect is achieved in the vertical dimension by the doped drain columns penetrating through the drift region, eliminating the need for lateral area expansion.
3Reliability
If gate oxide layer with staircase shape is fabricated, then thickness of gate oxide layer between gate electrode and drain region is increased, but manufacturing cost is increased
Solution Approach 1:
The patent achieves increased breakdown voltage by changing the doping concentration parameter of the drain region rather than changing the gate oxide thickness. By adjusting the doping concentration in the vertically extended drain structure, the electric field distribution is optimized without requiring complex multi-step oxidation processes or additional photomasks.
Solution Approach 2:
The patent extracts the breakdown voltage enhancement mechanism from the gate oxide layer and relocates it to the drain region doping structure. Instead of modifying the gate oxide to achieve high breakdown voltage, the solution is extracted and implemented through vertically extended doped drain columns, simplifying the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases breakdown voltage while maintaining or reducing the channel length, thus enhancing the performance of MOS transistors without the need for additional processing steps or increased costs.
Implementation Method 1
modifying the current path and electric field distribution
Implementation Method 2
a doping concentration of the at least one first drift region is less than a doping concentration of the at least one first doped region
Data Source
Figure 1A
Figure 1B
Figure 2
AI summary
High voltage semiconductor device and manufacturing method thereof are disclosed. The high voltage semiconductor device includes a semiconductor substrate, a gate structure, at least one first isolation structure and at least one second isolation structure, and at least one first drift region. The gate structure is disposed on the semiconductor substrate. The first isolation structure and the second isolation structure are disposed in an active area of the semiconductor substrate at a side of the gate structure. An end of the second isolation structure is disposed between the first isolation structure and the gate structure, and an end of the first isolation structure is disposed between the first doped region and the second isolation structure. A bottom of the at least one first isolation structure and a bottom of the at least one second isolation structure are deeper than a bottom of the first drift region.