Mosaic Focal Plane Array With Interposer for Optical Continuity
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Solution Overview
Problem
Large format focal plane arrays face challenges in achieving high yield due to the scaling of electrical yield with die area, leading to difficulties in fitting 3D integrated circuitry within the required pixel area, and previous solutions like mosaic arrays and mechanical dithering result in lower frame rates or slower image capture.
Innovation Solution
A mosaic integrated circuit device composed of small format, high yield integrated circuit tiles arranged to form a large format array, with an interposer adjusting the detector array pitch to minimize optical gaps and ensure optical continuity, using composite wafer construction and 3D integrated circuit tiles to maximize yield and minimize peripheral area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a large single integrated circuit device is used to create large format FPA, then the FPA can cover a larger field of view, but the electrical yield decreases significantly due to the inverse scaling with die area
Solution Approach 1:
The large format FPA is divided into multiple smaller integrated circuit tiles (e.g., 1k×1k tiles) that are arranged in a mosaic configuration. Each tile has its own detector array and readout circuitry, allowing individual tiles to be manufactured with high yield. The tiles are then assembled to form the complete large format array, overcoming the yield penalty of large single-die fabrication.
2Adaptability or versatility
If 3D integrated circuit is used to fit required circuitry into available pixel area, then functionality is improved, but the yield of each layer is multiplied together causing overall yield to decrease
Solution Approach 1:
The 3D integrated circuit is segmented into multiple smaller 3D tile units, each with stacked layers containing detector, readout circuitry, and signal processing functions. By reducing the size of each 3D tile, the yield of individual layers is improved, and the multiplicative yield penalty is reduced. Multiple high-yield tiles are then assembled to achieve the required total functionality.
3Reliability
If mosaic array of smaller hybrid detectors is used to increase yield, then manufacturing yield is improved, but optical gaps appear between mosaic detectors reducing image quality
Solution Approach 1:
An interposer is introduced as an intermediary substrate between the mosaic array of detector tiles and the readout circuitry. The interposer provides precise alignment features and interconnection structures that bridge the gaps between individual tiles, enabling optical continuity across the mosaic array while maintaining the manufacturing yield benefits of using smaller discrete tiles.
4Area of stationary object
If mechanical dithering is used to fill in gaps between mosaic detectors, then optical coverage is improved, but the overall frame rate decreases
Solution Approach 1:
The interposer provides fixed alignment and connection structures that eliminate the need for mechanical dithering. By precisely positioning detector tiles and providing stable interconnections during readout, the system achieves complete optical coverage without requiring time-consuming mechanical movements, thereby maintaining high frame rates.
5Area of stationary object
If stare-step approach is used to allow single smaller sensor to cover larger field of regard, then field of view is increased, but the overall frame or revisit rate becomes slower
Solution Approach 1:
Instead of using a single sensor with mechanical scanning, the system segments the field of view across multiple detector tiles arranged in a mosaic array. All tiles can be read out simultaneously in parallel, providing a large field of view while maintaining high frame rates without the need for time-sequential stare-step scanning.
Data Source
AI summary
A focal plane array includes a mosaic integrated circuit device having a plurality of discrete integrated circuit tiles mounted on a motherboard. The focal plane array includes an optically continuous detector array electrically connected to the mosaic integrated circuit device with an interposer disposed therebetween. The interposer is configured to adjust a pitch of the continuous detector array to match a pitch of each of the plurality of discrete integrated circuit tiles so that the optical gaps between each of the plurality of integrated circuit tiles on the motherboard are minimized and the detector array is optically continuous, having high yield over the large format focal plane array.