MOSFET Spacer Air-Gap Structure for Faster RF Switching
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Solution Overview
Problem
Parasitic and overlap capacitances in MOSFET devices, particularly those operating in radio frequency, degrade performance by slowing switching speed due to capacitive effects across sidewall spacers and gate oxide dielectric layers, with high-k gate and spacer materials exacerbating fringing capacitance issues.
Innovation Solution
Formation of air gaps in sidewall spacers made from higher dielectric materials like silicon oxide or silicon nitride, reducing the dielectric constant and thereby lowering junction, overlap, and fringing capacitances, which improves switching speed and short-channel performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k gate and spacer materials are used to improve gate control and reduce leakage, then device reliability is improved, but fringing capacitance increases which degrades switching speed
Solution Approach 1:
The patent applies local quality by creating air gaps specifically in the spacer regions adjacent to the gate, while maintaining high-k materials in other critical areas. This localized modification reduces fringing capacitance without compromising overall gate control, as the air gaps are strategically positioned only where they most effectively reduce parasitic effects.
Solution Approach 2:
The patent changes the dielectric parameter of the spacer material from high-k to air (k=1) in specific regions. This parameter change directly reduces the fringing capacitance formed between the gate and source/drain regions, thereby improving switching speed while maintaining reliability through controlled implementation.
2Power
If larger overlap areas are used to improve current drive, then device power is improved, but overlap capacitance increases which slows switching speed
Solution Approach 1:
The patent applies local quality by introducing air gaps specifically in the overlap regions between the gate and source/drain extensions. This localized dielectric modification reduces overlap capacitance in the critical fringing field areas while maintaining the necessary overlap area for current drive, thus improving switching speed without sacrificing power capability.
3Reliability
If deeper junctions are used to improve breakdown voltage, then device reliability is improved, but junction capacitance increases which degrades high-frequency performance
Solution Approach 1:
The patent applies local quality by creating air gaps in the spacer regions above the junctions, which reduces the parasitic capacitance associated with deeper junctions. This localized modification allows the device to maintain deep junctions for breakdown voltage while reducing the capacitive effects that limit high-frequency performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of air gaps in MOSFET devices reduces parasitic and fringing capacitances, enhancing switching speed and maintaining or improving short-channel performance by lowering the dielectric constant between charge-carrying plates, thus addressing the performance degradation caused by capacitance.
Implementation Method 1
Parasitic/overlap capacitances resulting from capacitive effects across sidewall spacers and/or from the gate oxide dielectric layer degrade the performance of metal-oxide semiconductor field effect transistor (MOSFET) devices
Implementation Method 2
Formation of air gaps in sidewall spacers made from higher dielectric materials like silicon oxide or silicon nitride, reducing the dielectric constant and thereby lowering junction, overlap, and fringing capacitances
Data Source
AI summary
A transistor device and method of making the same are disclosed. The transistor device includes one or more air gaps in one or more sidewall spacers. The one or more air gaps may be located adjacent the gate and/or above the source or drain regions of the device. Various embodiments may include different combinations of air gaps formed in one or both sidewall spacers. Various embodiments may include air gaps formed in one or both sidewall spacers adjacent to the gate and/or above the source or drain regions of the device. The formation of the air gaps may reduce unwanted parasitic and/or fringing capacitance.