Power MOSFET Package Al Ribbon Source Bonding
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Solution Overview
Problem
The existing small surface mounted packages for power MOSFETs face challenges in reducing contact resistance between the source pad and Au wire or source lead, limiting the reduction of on-resistance due to a small contact area, which also increases the package size and affects production yield and cost.
Innovation Solution
The use of an Al ribbon with a wider area than the Au wire for coupling the source pad to the source lead, combined with an optimized Ag paste with specific elastic modulus and shear strength to prevent cracking during bonding, and the formation of a Pd film on the lead frame for improved adhesion, allowing for a larger bonding area and reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Au wire is used to couple source pad to source lead, then electrical connection is achieved, but contact resistance cannot be reduced sufficiently due to small contact area
Solution Approach 1:
An Al ribbon is introduced as an intermediary component between the source pad and source lead. The Al ribbon has a wider area than Au wire, providing a larger contact area that reduces contact resistance while maintaining electrical connection functionality.
Solution Approach 2:
The patent changes the physical parameters of the bonding material from thin Au wire to wider Al ribbon. This parameter change increases the contact area and reduces contact resistance, directly addressing the technical contradiction.
2Reliability
If area of source pad is increased to accommodate multiple Au wires, then contact resistance may be reduced, but size of silicon chip and mounting area increase
Solution Approach 1:
The Al ribbon acts as a mediator that provides large contact area without requiring enlargement of the source pad. The ribbon's wider area compensates for the limited pad size, reducing contact resistance while maintaining compact chip dimensions.
3Reliability
If Ag paste is used for bonding silicon chip to die pad, then electrical and mechanical connection is achieved, but cracking occurs during bonding process
Solution Approach 1:
The patent optimizes the physical and chemical parameters of the Ag paste, including particle size distribution, binder composition, and metallic content. These parameter changes improve the paste's flow characteristics and adhesion properties, enabling bonding without cracking.
Solution Approach 2:
The Ag paste is formulated as a composite material containing Ag particles, binder, and other additives in specific ratios. This composite structure provides both bonding strength and crack resistance during the bonding process.
4Ease of manufacture
If standard lead frame structure is used, then manufacturing is simplified, but adhesion and bonding performance are insufficient
Solution Approach 1:
The patent applies a Pd film coating to specific areas of the lead frame where bonding occurs. This local quality enhancement improves adhesion and bonding performance at critical interfaces without complicating the overall lead frame structure or manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the on-resistance of the semiconductor device, improves production yield and reliability, and decreases manufacturing costs by increasing the bonding area and preventing cracks in the Ag paste, while also enabling size reduction and Pb elimination from the semiconductor device.
Implementation Method 1
The backside of the semiconductor chip forming a drain of the power MOSFET is coupled onto the die pad portion with an Ag paste
Implementation Method 2
the source lead is coupled to the source pad with an Al ribbon
Implementation Method 3
the formation of a Pd film on the lead frame for improved adhesion
Data Source
AI summary
To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.