MOSFET Arithmetic Circuit for Low-Loss Processing-in-Memory

The patent extracts and eliminates the conversion stages (digital-to-analog and analog-to-digital) from the in-memory calculation process. By performing calculations directly on digital signals within the memory array using CMOS circuits, the quantization errors introduced by conversion are completely removed while preserving full calculation capability.

The patent replaces the traditional mechanical/electrical conversion system with a purely digital electronic system. Instead of converting between analog and digital domains, the invention uses digital signal processing directly in the memory, substituting the conversion mechanism with direct digital computation using CMOS logic circuits.

The patent merges multiple output signal lines into a single shared output line for each arithmetic unit. By using timing control to multiplex the output, multiple calculation results are transmitted through one line at different time slots, reducing chip area and noise while maintaining calculation speed through parallel processing architecture.

The patent implements periodic timing control signals that activate different arithmetic units at different time slots. This periodic activation allows multiple units to share a common output line without conflict, as each unit outputs its result during its designated time period, thus reducing wiring complexity while preserving parallel computation capability.

The patent combines multiple output signal paths into a single shared output line, reducing the total number of signal lines and associated power consumption. The merging is achieved through time-division multiplexing where different arithmetic units use the shared line at different times, maintaining throughput while minimizing energy loss from redundant wiring.

The single output line serves multiple arithmetic units universally, functioning as a shared resource rather than dedicated lines for each unit. This multi-functional use of the output line reduces the overall system power consumption while maintaining the ability to handle multiple calculation streams through temporal multiplexing.

The patent uses periodic timing control signals to manage the sharing of output lines among multiple arithmetic units. This temporal coordination allows flexible calculation configurations to be achieved through software-controlled timing rather than complex physical wiring, significantly reducing device complexity while maintaining adaptability.

The patent introduces dynamic timing control that allows the system to flexibly allocate output line usage based on computational needs. Rather than fixed dedicated connections, the system dynamically assigns time slots to different arithmetic units, providing calculation flexibility through software control while minimizing physical wiring complexity.