MOSFET Structure for Avalanche Breakdown Suppression

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Solution Overview

Problem

Semiconductor devices such as MOSFETs face breakdown issues due to avalanche breakdown, which can lead to dielectric breakdown of the gate insulating layer and reliability concerns, especially in power conversion applications.

Innovation Solution

The semiconductor device design includes a specific structure with a p+-type semiconductor region, a conductive part, and an n+-type semiconductor region, where the n+-type semiconductor region contacts the p+-type semiconductor region, reducing the electric field strength and suppressing avalanche breakdown, thereby enhancing the breakdown voltage and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional MOSFET structure is used, then the device can perform power conversion, but avalanche breakdown occurs leading to dielectric breakdown of the gate insulating layer

Engineering Contradiction:
Improvebreakdown voltageVSAvoidavalanche breakdown
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

An n-type semiconductor layer is introduced as an intermediary between the drift region and the gate insulating layer. This intermediate layer acts as a mediator that modifies the electric field distribution, preventing direct avalanche breakdown at the gate insulating layer while maintaining power conversion functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies different doping concentrations and types in different regions: the n-type semiconductor layer has a specific doping concentration (1×10^16 to 1×10^18 atoms/cm³) that differs from both the drift region and the gate insulating layer interface. This local variation in material properties optimizes the electric field distribution to suppress avalanche breakdown at critical locations.

Inventive Principle:
Principle #3Local quality

2Reliability

If the electric field strength is reduced to suppress avalanche breakdown, then reliability improves, but on-resistance increases

Engineering Contradiction:
Improvesuppression of avalanche breakdownVSAvoidon-resistance
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The patent optimizes the doping concentration of the n-type semiconductor layer within a specific range (1×10^16 to 1×10^18 atoms/cm³). By carefully controlling this parameter, the electric field is sufficiently reduced to suppress avalanche breakdown while maintaining low on-resistance through adequate carrier concentration.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The n-type semiconductor layer extends in the thickness direction (vertical dimension) with a specific thickness (0.1 to 10 μm). This dimensional approach allows the electric field to be managed through the thickness dimension while maintaining horizontal current flow properties that keep on-resistance low.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed design effectively suppresses avalanche breakdown and dielectric breakdown, improving the reliability and reducing on-resistance of the semiconductor device while maintaining a high breakdown voltage.

Implementation Method 1

The n+-type semiconductor region contacts the p+-type semiconductor region, reducing the electric field strength and suppressing avalanche breakdown

Methodology Applied
Scientific EffectAvalanche breakdown: Avalanche Breakdown

Data Source

PatentUS20230290850A1Semiconductor device and semiconductor package
Publication Date: 2023.09.14 KK TOSHIBA
  • US20230290850A1 patent drawing
  • US20230290850A1 patent drawing
  • US20230290850A1 patent drawing

AI summary

According to one embodiment, a semiconductor device includes first and second electrodes, first to sixth semiconductor regions, a gate electrode, and a conductive part. The first semiconductor region is located on the first electrode. The first semiconductor region includes first and second regions. The second semiconductor region is located on the first region. The gate electrode is located on the second semiconductor region with a gate insulating layer interposed. The third semiconductor region is located on the first region and is separated from the second semiconductor region. The conductive part is located on the third semiconductor region with an insulating layer interposed. The fourth semiconductor region is located on the second region. The fifth semiconductor region is located on a portion of the fourth semiconductor region. The sixth semiconductor region contacts the third semiconductor region. The second electrode is located on the fourth and fifth semiconductor regions.