Trench MOSFET Gate Buffer Layer Prevents Over-Etching Shorts
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Solution Overview
Problem
In trench MOSFETs, over etching during silicon etch processes can lead to shorts between the gate and drain due to the higher etch rate of heavily doped polysilicon, causing reliability issues and threshold voltage non-uniformity, especially in shallower trenches.
Innovation Solution
Incorporating an etching buffer layer in the trench gate, composed of undoped or lightly doped polysilicon, which slows down the etching process and prevents over etching, while maintaining the gate resistance by using a combination of doped and undoped polysilicon layers in the gate trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If heavily doped polysilicon is used to fill the gate trench, then the gate conductivity is improved, but the etching rate increases causing over etching and gate-drain shorts
Solution Approach 1:
The gate conductive layer is segmented into two distinct parts: a first gate conductive layer (heavily doped polysilicon) and a second gate conductive layer (buffer layer with different doping). This segmentation allows each layer to have different etching characteristics, with the second layer acting as a buffer to prevent over-etching through the first layer to the epitaxial layer.
Solution Approach 2:
The second gate conductive layer serves as an intermediary layer between the first gate conductive layer and the epitaxial layer. During etching, this intermediate layer slows down the etching process, preventing direct contact between the etching tool and the epitaxial layer, thus avoiding gate-drain shorts.
2Ease of manufacture
If the trench depth is reduced, then the manufacturing complexity is lowered, but the risk of gate-drain shorts increases due to higher etch rate
Solution Approach 1:
The second gate conductive layer is deposited in advance during the gate formation process, creating a protective buffer before any etching occurs. This preliminary action ensures that even in shallower trenches, the etching process will not directly reach the epitaxial layer, maintaining reliability without requiring deeper trenches.
3Reliability
If doped polysilicon is used in the gate trench, then the gate conductivity is improved, but dopant outgassing causes threshold voltage non-uniformity
Solution Approach 1:
The gate conductive layer is divided into two segments with different doping levels. The first layer provides necessary conductivity, while the second layer (buffer layer) has different doping characteristics that reduce dopant outgassing, thereby stabilizing the threshold voltage.
Solution Approach 2:
Different regions of the gate conductive layer have different doping qualities. The first gate conductive layer has heavy doping for conductivity, while the second gate conductive layer has different doping levels to minimize dopant outgassing effects locally at the interface with the epitaxial layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The buffer layer effectively prevents gate-drain shorts and stabilizes threshold voltage, enhancing yield and reliability without affecting gate resistance, and reduces dopant outgassing-related issues.
Implementation Method 1
the buffer layer deposited on wafer backside simultaneously also avoids threshold voltage non-uniformity and instability across wafer and wafer to wafer due to heavily dopant outgassing from the doped poly on wafer backside
Data Source
AI summary
The present invention is to provide a trench MOSFET with an etching buffer layer in a trench gate, comprising: a substrate which has a first surface and a second surface opposite to each other and comprises at least a drain region, a gate region, and a source region which are constructed as a plurality of semiconductor cells with MOSFET effect; a plurality of gate trenches, each of which is extended downward from the first surface and comprises a gate oxide layer covered on a inner surface thereof and a gate conductive layer filled inside, comprised in the gate region; at least a drain metal layer formed on the second surface according to the drain region; at least a gate runner metal layer formed on the first surface according to the gate region; and at least a source metal layer formed on the first surface according to the source region; wherein the gate trenches distinguished into at least a second gate trench formed at a terminal of the source region and at least a first gate trenches wrapped in the source region; and the second gate trench comprises a gate contact hole which is filled with metal to form a gate metal contact plug, and a gate buffer layer which is formed in the gate conductive layer at the bottom of the gate contact hole in the second gate trench to prevent from over etching, causing gate-drain shortage.