Power MOSFET Buried Charge Compensation Floating Ring
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Solution Overview
Problem
Conventional power MOSFET manufacturing facilities face challenges in producing superjunction MOSFETs due to the need for deep trench etching and epitaxial silicon layer growth, leading to high fabrication costs and contamination issues, as well as equipment and expertise limitations, making it difficult to manufacture devices with multiple epitaxial layers.
Innovation Solution
A novel power field effect transistor device with buried charge compensation layers and a floating P-type surface ring structure, which achieves a high breakdown voltage of 100 volts without requiring deep trench etching or multiple epitaxial layers, allowing for manufacturing in facilities lacking specific equipment and expertise, by using a substrate with two epitaxial layers and concentric P-type surface rings connected by a metal bridging member.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep trench etching and multiple epitaxial layer deposition are used to manufacture superjunction MOSFETs, then breakdown voltage and on-resistance performance are improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the deep trench etching step from the manufacturing process. Instead of forming deep trenches and filling them with P-type silicon, the invention uses a simplified structure with P-type surface regions directly formed on the N-type epitaxial layer, removing the complex trench formation and filling operations while maintaining the charge balancing function.
Solution Approach 2:
The patent segments the device into distinct functional regions: an N-type epitaxial layer and P-type surface regions formed in specific patterns. This segmentation allows each region to be optimized independently and simplifies the manufacturing process by avoiding the need for deep trench formation and complex multi-layer epitaxial growth.
2Reliability
If deep trench etching and multiple epitaxial layer deposition are used to manufacture superjunction MOSFETs, then breakdown voltage and on-resistance performance are improved, but manufacturing cost increases
Solution Approach 1:
The patent removes the expensive deep trench etching and multiple epitaxial layer deposition steps from the manufacturing process. The simplified structure requires fewer fabrication steps, reducing equipment usage, processing time, and material costs while achieving comparable electrical performance through alternative structural design.
Solution Approach 2:
The patent employs a simpler, more disposable manufacturing approach by using standard epitaxial layer deposition followed by P-type region formation, avoiding the need for expensive deep trench etching equipment and complex multi-layer growth processes. This makes the manufacturing more accessible and cost-effective.
3Reliability
If multiple epitaxial layers are deposited to form superjunction MOSFETs, then device performance is improved, but equipment requirements and contamination risks increase
Solution Approach 1:
The patent extracts and eliminates the need for multiple epitaxial layer depositions and deep trench formation steps. By using a simplified structure with P-type surface regions on an N-type epitaxial layer, the invention reduces the number of fabrication steps, minimizing opportunities for contamination and reducing equipment requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves a reduced drain-to-source on-resistance and high breakdown voltage, enabling cost-effective manufacturing and operation, while avoiding the contamination and equipment limitations associated with traditional superjunction MOSFET production.
Implementation Method 1
Regions of P type dopants are implanted into the top surface of EPI#1
Implementation Method 2
After many such epitaxial deposition and implant steps, the P type dopants are made to diffuse so that the vertically oriented P type charge balancing columns 102 and 103 are formed
Implementation Method 3
an N− type epitaxial semiconductor layer EPI#1 on an N+ type wafer substrate 104
Data Source
AI summary
Stripe-shaped surface transistor structures of a power MOSFET are disposed over an array of parallel-extending P type Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs). The power MOSFET has two and only two epitaxial semiconductor layers, and the BSSCCRs are disposed at the interface between these layers. Looping around the area occupied by these parallel-extending BSSCCRs is a P type ring-shaped BSSCCR. At the upper semiconductor surface are disposed three P type surface rings. The inner surface ring and outer surface ring are coupled together by a bridging metal member, but the center surface ring is floating. The bridging metal member is disposed at least in part over the ring-shaped BSSCCR. The MOSFET has a high breakdown voltage, a low RDS(ON), and is acceptable and suitable for manufacture at semiconductor fabrication plants that cannot or typically do not make superjunction MOSFETs.