MOSFET Parasitic Capacitance Cancellation Using Negative Impedance
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Solution Overview
Problem
The parasitic capacitances of metal oxide semiconductor field effect transistors (MOSFETs) affect the performance of circuits due to their variation with bias voltages, which existing technologies have not adequately addressed.
Innovation Solution
A parasitic capacitance cancellation circuit and method utilizing a first transistor, couplers, and a negative impedance generator to couple and generate negative impedance, adjusting and canceling the parasitic capacitance to make it less affected by bias voltage variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MOSFETs are used in circuits, then device functionality is achieved, but parasitic capacitances affect circuit performance
Solution Approach 1:
The patent introduces a negative impedance generator that produces a negative impedance signal to counteract the parasitic capacitance. By converting the harmful capacitive effect into a beneficial cancellation through negative impedance, the parasitic capacitance is neutralized, improving circuit performance without removing the MOSFET itself
Solution Approach 2:
The negative impedance generator is configured to generate a counteracting signal before the parasitic capacitance can degrade circuit performance. The couplers transmit signals that are processed to create a preliminary opposing effect that cancels the parasitic capacitance impact in advance
2Reliability
If parasitic capacitance cancellation is implemented, then circuit performance is improved, but device complexity increases
Solution Approach 1:
The negative impedance generator serves multiple functions: it generates the negative impedance signal, processes it through couplers, and cancels the parasitic capacitance effect. This multi-functional approach consolidates the cancellation mechanism into a single integrated component rather than requiring multiple separate elements
Solution Approach 2:
The couplers act as intermediary elements that efficiently transmit signals between the MOSFET and the negative impedance generator. These intermediaries facilitate the cancellation process without requiring direct complex connections, simplifying the overall circuit architecture while maintaining effectiveness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The equivalent parasitic capacitance is reduced and remains nearly unaffected by variations in bias voltage, thereby improving circuit performance.
Implementation Method 1
The negative impedance generator is configured to generate and provide a negative impedance to the control terminal of the first transistor to cancel a parasitic capacitance of the first transistor
Data Source
AI summary
A parasitic capacitance cancellation circuit includes a first transistor, a first coupler, a second coupler, and a negative impedance generator. The first transistor includes a first terminal, a control terminal, and a second terminal. The first coupler is configured to couple the control terminal of the first transistor and the first terminal of the first transistor. The second coupler is configured to couple the control terminal of the first transistor and the second terminal of the first transistor. The negative impedance generator is configured to generate and provide a negative impedance to the control terminal of the first transistor to cancel a parasitic capacitance of the first transistor.