MOSFET Capacitive Voltage Divider with Reverse-Biased Junction Diodes
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Solution Overview
Problem
Transistor junction diodes in MOSFET-based capacitive voltage dividers exhibit non-linear characteristics, leading to variable input capacitance and attenuation, which complicates gain control in RF systems and increases noise figures due to junction capacitance.
Innovation Solution
The implementation of a capacitive voltage divider circuit using MOSFETs with reverse-biased junction diodes to operate in a more linear region, reducing junction capacitance and maintaining constant input capacitance by switching capacitors in and out of the circuit, and using shared n-wells to minimize n-well-diode capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If MOSFETs are used in capacitive voltage divider circuits, then the circuit can be implemented with standard semiconductor devices, but the junction diodes formed in the MOSFETs exhibit non-linear characteristics that cause variable input capacitance and attenuation
Solution Approach 1:
An n-well is introduced as an intermediary structure between the p-substrate and the PMOS transistor. This n-well acts as a buffer region that isolates the PMOS transistor from direct interaction with the p-substrate, thereby eliminating the formation of unwanted p-n junction diodes at the transistor-substrate interface while maintaining the beneficial electrical characteristics of the MOSFET structure.
Solution Approach 2:
The problematic p-n junction diode structure is extracted or removed from the circuit by preventing its formation through proper substrate-well-transistor configuration. The invention extracts the harmful non-linear diode effect from the otherwise useful MOSFET structure, allowing the circuit to benefit from MOSFET linearity without suffering from junction diode non-linearity.
2Object-affected harmful factors
If transistor sizes are reduced to minimize junction capacitance, then noise figures improve, but the non-linear effects of junction diodes become more significant
Solution Approach 1:
The n-well serves as a mediator that decouples the PMOS transistor from the p-substrate, preventing the formation of non-linear junction diodes. This allows transistors to be sized optimally for low noise performance without the penalty of increased non-linear junction capacitance effects, as the n-well isolation eliminates the problematic diode structures that would otherwise dominate the electrical behavior.
3Ease of manufacture
If junction diodes are present in MOSFET structures, then the transistors can be fabricated using standard p-n junction processes, but the diodes create directionality of current flow and non-linear capacitance that complicate circuit operation
Solution Approach 1:
The n-well is positioned as an intermediary layer between the p-substrate and PMOS transistor, maintaining compatibility with standard semiconductor fabrication processes while simultaneously preventing the formation of non-linear junction diodes. This intermediary structure preserves the ease of manufacturing through conventional processes while eliminating the operational complications of unwanted diode effects.
Solution Approach 2:
The invention applies local quality modification by creating an n-type region (n-well) in a specific location (within the p-substrate beneath the PMOS transistor) to alter the electrical characteristics locally. This localized modification prevents diode formation only where needed, maintaining standard fabrication processes elsewhere in the device while improving circuit operation in the critical transistor region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves a more linear operation of the capacitive voltage divider, reducing noise figures and allowing for smaller transistor sizes, while maintaining constant input capacitance over a wide gain control range, thereby improving the Quality Factor and reducing losses.
Implementation Method 1
reverse-biased junction diodes to operate in a more linear region, reducing junction capacitance
Implementation Method 2
capacitive voltage divider circuit using MOSFETs with reverse-biased junction diodes
Data Source
AI summary
Methods and apparatus for capacitive voltage division are provided, an example apparatus having an input and an output and including a first switched capacitor circuit. In some embodiments, the capacitive voltage divider includes first and second MOSFETs. A first capacitor is coupled between the drain of the first MOSFET and the input to the capacitive voltage divider. A first circuit coupled to the drain of the first MOSFET is configured to pull down the drain of the first MOSFET and thus apply a reverse bias to a first junction diode internal to the first MOSFET between the drain and the bulk of the first MOSFET. A second capacitor is coupled between the source of the first MOSFET and the drain of the second MOSFET. A second circuit is configured to reverse bias a second junction diode between the drain and bulk of the second MOSFET.