Integrated MOSFET Capacitor Layout for Lower Gate-Drain Capacitance

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Solution Overview

Problem

Conventional field plate structures in LDMOS devices introduce parasitic feedback capacitance, which negatively impact high-frequency performance, particularly in high-speed switching applications, despite enhancing breakdown voltage and reducing on-resistance.

Innovation Solution

An integrated capacitor is designed with a doped semiconductor layer, an insulating layer, and a polysilicon layer, forming an inversion layer and a doped region adjacent to the drain or source region, reducing parasitic gate-to-drain capacitance without degrading breakdown voltage or on-resistance, compatible with CMOS fabrication technology.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If a field plate structure is used in LDMOS device, then breakdown voltage is enhanced and on-resistance is reduced, but parasitic gate-to-drain capacitance increases

Engineering Contradiction:

Improvebreakdown voltageVSAvoidparasitic gate-to-drain capacitance

Core Design Contradiction:

StrengthVSObject-affected harmful factors

Solution Approach 1:

The gate structure is segmented into two independent parts: the main gate and the field plate. By making them electrically independent through separate connections, the field plate can be optimized for breakdown voltage enhancement while the main gate can be optimized for minimizing parasitic capacitance. This segmentation allows independent optimization of each component's function.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The field plate function is extracted from the conventional gate structure and made into a separate, independently controllable element. This extraction allows the field plate to be specifically optimized for electric field modulation and breakdown voltage enhancement without being constrained by the gate's primary function of controlling channel current, thereby reducing unwanted parasitic effects.

Inventive Principle:

Principle #2Taking out (Extraction)

2Reliability

If field plate area is increased to reduce on-resistance, then electron accumulation in drift region improves, but parasitic feedback capacitance increases

Engineering Contradiction:

Improveon-resistanceVSAvoidparasitic feedback capacitance

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the gate structure are given different electrical properties and functions. The main gate region is optimized for low parasitic capacitance with appropriate dimensions and positioning, while the field plate region is optimized for electric field modulation and breakdown voltage enhancement. Each region has tailored dimensions, doping, and connection to achieve its specific local function.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution provides a high-value capacitor with a small footprint, lower switching loss, and enhanced high-frequency performance, suitable for integration with DC-DC voltage converters.

Implementation Method 1

An inversion layer is formed in the doped semiconductor layer, beneath the insulating layer and proximate the upper surface of the doped semiconductor layer, as a function of an applied voltage between the first and second plates of the capacitor

Methodology Applied

Scientific EffectInversion layer formation: Capacitance

Implementation Method 2

The doped region is electrically connected to the inversion layer

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS12446298B2Enhanced capacitor for integration with metal-oxide semiconductor field-effect transistor

Publication Date: 2025.10.14 SHANGHAI BRIGHT POWER SEMICONDUCTOR CO LTD

AI summary

A capacitor is provided for integration with a MOSFET device(s) formed on the same substrate. The capacitor comprises a first plate including a doped semiconductor layer of a first conductivity type, an insulating layer formed on an upper surface of the doped semiconductor layer, and a second plate including a polysilicon layer formed on an upper surface of the insulating layer. An inversion layer is formed in the doped semiconductor layer, beneath the insulating layer and proximate the upper surface of the doped semiconductor layer, as a function of an applied voltage between the first and second plates of the capacitor. At least one doped region of a second conductivity type, opposite the first conductivity type, is formed in the doped semiconductor layer adjacent to a drain and/or source region of the first conductivity type formed in the MOSFET device. The doped region is electrically connected to the inversion layer.