Power MOSFET Capping Layer for Dopant Up-Diffusion Suppression
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Solution Overview
Problem
The challenge in fabricating MOSFET devices is to minimize specific on-resistance (Rsp(on)) and control dopant profiles effectively, as fast-diffusing dopants like phosphorus lead to up-diffusion issues and substrate resistivity variations, making it difficult to achieve low drain-to-source resistance (Rds(on)) and consistent device performance.
Innovation Solution
An ion-implanted capping layer with a slow-diffusing dopant like arsenic is introduced between the lightly doped epitaxial layer and the highly doped silicon substrate, allowing for precise control of the dopant profile and minimizing up-diffusion, resulting in a steeper gradient and lower Rds(on) values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fast-diffusing dopants like phosphorus are used in the substrate, then substrate resistivity can be reduced, but up-diffusion occurs during fabrication leading to inconsistent dopant profiles and higher Rds(on)
Solution Approach 1:
A capping layer is introduced as an intermediary between the lightly doped epitaxial layer and the highly doped substrate. This capping layer acts as a diffusion barrier that prevents fast-diffusing dopants from the substrate from up-diffusing into the epitaxial layer, thereby maintaining dopant profile consistency while allowing the substrate to maintain its low resistivity
Solution Approach 2:
The patent applies different doping strategies to different regions: the substrate uses fast-diffusing dopants for low resistivity, while the capping layer uses slow-diffusing dopants to create a localized diffusion barrier. This local differentiation allows each region to optimize its electrical properties without compromising the other
2Reliability
If fast-diffusing dopants are used to reduce substrate resistivity, then electrical conductivity improves, but up-diffusion during fabrication increases Rds(on)
Solution Approach 1:
The capping layer serves as a protective intermediary that blocks the harmful up-diffusion of fast-diffusing dopants from the substrate into the epitaxial layer. This allows the substrate to maintain its high electrical conductivity through fast-diffusing dopants while preventing the generation of harmful resistance in the channel region
Solution Approach 2:
The patent converts the potentially harmful effect of fast-diffusing dopants into a benefit by confining them to the substrate region where their high diffusivity is advantageous for achieving low bulk resistivity, while the capping layer prevents this same property from causing harmful up-diffusion into the epitaxial layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the drain-to-source resistance (Rds(on)) of MOSFET devices by containing phosphorus up-diffusion within the epitaxial layer, ensuring consistent dopant profiles and improved switching performance.
Implementation Method 1
An ion-implanted capping layer with a slow-diffusing dopant like arsenic is introduced between the lightly doped epitaxial layer and the highly doped silicon substrate
Implementation Method 2
fast-diffusing dopants like phosphorus lead to up-diffusion issues
Data Source
AI summary
A method includes forming an ion-implanted capping layer in a first epitaxial layer disposed on a silicon substrate. The ion-implanted capping layer is doped with a second dopant of a same conductivity type as a first dopant in the silicon substrate. The second dopant has a lower diffusivity than the diffusivity of the first dopant. The ion-implanted capping layer has a thickness configured to contain up-diffusion of the first dopant from the silicon wafer in the first epitaxial layer in thermal processes for fabricating a vertical MOSFET device in the substrate. The ion-implanted capping layer is configured to limit up-diffusion of the first dopant from the silicon wafer through the ion-implanted capping layer into a second epitaxial layer such that a concentration of the first dopant in the second epitaxial layer is lower than a concentration of the first dopant in the first epitaxial layer.