MOSFET Cell Layout for Lower ON-State Resistance
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Solution Overview
Problem
Conventional semiconductor devices, such as SiC MOSFETs, face challenges in minimizing ON-state resistance while maintaining switching speed and avoiding increased OFF-state resistance, due to limitations in fabricating optimal cell geometries that maximize channel region area relative to n+/p-well and source contact regions.
Innovation Solution
The proposed solution involves arranging semiconductor device cells with increased channel region area and density, oriented to take advantage of lower resistance paths across the wafer, and optimizing the relative proportions of channel, n+/p-well, and source contact regions to reduce ON-state resistance, while maintaining or minimizing OFF-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional MOSFET cell geometries are used with standard proportions of channel, n+/p-well, and source contact regions, then manufacturing is simplified, but ON-state resistance is higher than optimal
Solution Approach 1:
The patent applies local quality by varying the geometry and proportions of different regions within the MOSFET cell structure. Specifically, the channel region width, n+/p-well region dimensions, and source contact region sizes are optimized locally to minimize ON-state resistance. The cell geometry is tailored with specific width-to-length ratios for each region based on their individual resistance contributions, rather than using uniform proportions throughout the device.
2Loss of energy
If channel region area is increased to reduce ON-state resistance, then conduction losses decrease, but device area increases
Solution Approach 1:
The patent merges multiple cell structures into a unified power MOSFET device, arranging numerous individual transistor cells in parallel. This combining approach allows the total channel region area to be increased for lower conduction losses, while the current is distributed across multiple cells rather than concentrated in a single large device, effectively managing the area trade-off.
3Reliability
If cell geometry is optimized for minimum ON-state resistance, then electrical performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs parameter changes by systematically varying the geometric parameters of the MOSFET cell structure - including channel width, well region depth, contact region area, and cell pitch - to achieve optimal electrical performance. These parameters are carefully selected and adjusted during the design phase to balance performance requirements with manufacturability, ensuring that the optimized geometry can be realized through standard fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a net decrease in ON-state resistance compared to conventional designs, enhancing the electrical performance of semiconductor devices by reducing conduction losses and minimizing device size.
Implementation Method 1
Appropriate biasing creates an electrical field that attracts charge carriers into the channel which then provides a conductive path between the source and drain
Implementation Method 2
drain to source current conduction through the wafer, which eliminates current and reduces the on-state resistance
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
A semiconductor device cell (72) includes a semiconductor layer (2) having a surface (4) defining a series of steps, the steps oriented toward a first direction (23), a drift region (16) and a well region (18) defining a set of well region segments (17). A source region (20) is disposed adjacent to the well region (18) and surrounded by the well region (18). A channel region (28) defines a set of channel region segments (28a) proximal to the semiconductor layer surface (4), the channel region segments (28a) having a respective first longitudinal axis (31) extending in a second direction (25) transverse to the first direction (23). A periphery of the channel region segments (28a) are surrounded by the well region (18). The well region (18), source region (20), and channel region (28) cooperatively define a first axial length (D1) extending across the surface (4). The semiconductor layer surface (4) has a higher electrical resistance in the first direction (23) than in the second direction (25).