MOSFET Channel Structure Using {110} Planes to Limit Short-Channel Effects
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Solution Overview
Problem
The miniaturization of MOSFETs in semiconductor devices leads to a short channel effect, deteriorating their operating characteristics and necessitating improved methods for high integration and performance.
Innovation Solution
The semiconductor device incorporates a semiconductor substrate with {110} crystal planes, epitaxial layers, and specific channel patterns with protruding edges, along with a gate electrode and insulating layers, to enhance electrical characteristics and reliability, including a {110} crystal plane substrate and epitaxial layer with channel patterns that reduce surface scattering and improve carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET size is reduced to achieve high integration, then device density increases, but short channel effect deteriorates operating characteristics
Solution Approach 1:
The patent changes the crystal plane parameter from conventional {100} to {110} to improve carrier mobility and reduce surface scattering effects. This parameter change allows smaller channel lengths to maintain good operating characteristics, enabling higher integration density without suffering from short channel effects.
Solution Approach 2:
The patent introduces surface patterns with protruding edges that create three-dimensional carrier paths. By forming channels along inclined surfaces and utilizing vertical protrusions, the invention adds dimensional complexity to the traditionally planar channel structure, improving carrier transport while maintaining scaled dimensions.
2Reliability
If channel length is increased to improve carrier mobility, then surface scattering is reduced, but device area increases
Solution Approach 1:
The patent utilizes three-dimensional channel structures with vertical protrusions and inclined surfaces to extend the effective carrier path length without increasing the planar device footprint. The channel patterns include first and second surfaces connected through protruding edges, creating extended paths in the vertical dimension that improve mobility while maintaining compact area.
Solution Approach 2:
The surface patterns with protruding edges create curved and inclined carrier paths instead of straight linear channels. The carrier transport path follows the contours of the protruding edges and inclined surfaces, effectively increasing the path length within a compact area and reducing surface scattering effects.
Data Source
AI summary
Provided is a semiconductor device comprising: a semiconductor substrate; source/drain patterns spaced apart in a first direction on the semiconductor substrate; and channel patterns on the semiconductor substrate, wherein at least one of the channel patterns is between adjacent source/drain patterns among the source/drain patterns, wherein at least one of the channel patterns includes a plurality of semiconductor patterns, and the plurality of semiconductor patterns are spaced apart from each other in a second direction that is perpendicular to an upper surface of the semiconductor substrate, wherein the semiconductor substrate includes a {110} crystal plane, wherein at least one of the channel patterns includes a surface pattern, wherein the surface pattern includes first surfaces and second surfaces, wherein the first surfaces include protruding edges, wherein the second surfaces are respectively connected to the first surfaces through protruding edges, and wherein the protruding edges are arranged in a third direction.