Channel-Last MOSFET Threshold Voltage Variation Control
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Solution Overview
Problem
The reproducibility of threshold voltages among metal-oxide-semiconductor field effect transistors (MOSFETs) is undermined by random dopant fluctuations, random extension fluctuations, and line edge roughness, particularly as MOSFETs shrink in size, leading to increased variability and costs associated with advanced manufacturing processes like FinFETs and FDSOI.
Innovation Solution
A 'channel-last' process is introduced, where a lightly doped epitaxial layer is formed within a cavity over a heavily doped region, using low-temperature epitaxial growth, to minimize dopant diffusion and reduce variations in threshold voltage, while maintaining the cost advantages of standard bulk MOS manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFETs are shrunk in size to improve integration density, then productivity increases, but manufacturing precision deteriorates due to increased random dopant fluctuations and random extension fluctuations
Solution Approach 1:
The channel region is segmented into multiple doping zones: a first doped region with higher doping concentration and a second doped region with lower doping concentration. This segmentation allows the first region to provide robust electrostatic control while the second region maintains carrier mobility, thereby reducing threshold voltage variations without requiring further device scaling
Solution Approach 2:
Different regions of the MOSFET channel are assigned different doping qualities: the first doped region near the source/drain interfaces has higher doping concentration to suppress short-channel effects and reduce random extension fluctuations, while the second doped region in the channel center has lower doping concentration to maintain carrier mobility and reduce random dopant fluctuations. This local quality differentiation resolves the contradiction between size reduction and threshold voltage reproducibility
2Manufacturing precision
If advanced manufacturing processes like FinFET and FDSOI are adopted to reduce threshold voltage variations, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
Instead of using complex three-dimensional structures like FinFET or fully depleted SOI to control threshold voltage variations, this invention inverts the approach by using a planar MOSFET with a specially designed doping profile. The doping concentration varies laterally across the channel rather than vertically, achieving similar threshold voltage control with simpler device geometry and manufacturing processes
Solution Approach 2:
The invention changes the doping concentration parameter across the channel width, creating a graded doping profile where concentration varies from the source/drain interfaces toward the channel center. This parameter change allows control of threshold voltage and reduction of random fluctuations without adopting complex device architectures, thereby improving manufacturing precision while maintaining process simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces variations in threshold voltage, achieving reproducibility among identical transistors and minimizing thermal exposure, thus enhancing device performance and reducing the impact of random fluctuations and line edge roughness.
Implementation Method 1
a lightly doped epitaxial layer is formed within a cavity over a heavily doped region, using low-temperature epitaxial growth
Data Source
AI summary
Variation resistant metal-oxide-semiconductor field effect transistors (MOSFETs) are manufactured using a high-K, metal-gate ‘channel-last’ process. A cavity is formed between spacers formed over a well area having separate drain and source areas, and then a recess into the well area is formed. The active region is formed in the recess, comprising an optional narrow highly doped layer, essentially a buried epitaxial layer, over which a second un-doped or lightly doped layer is formed which is a channel epitaxial layer. The high doping beneath the low doped epitaxial layer can be achieved utilizing low-temperature epitaxial growth with single or multiple delta doping, or slab doping. A high-K dielectric stack is formed over the channel epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.