Modified MOSFET Channel Structure for Sub-Surface Leakage Blocking
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Solution Overview
Problem
Shrinking the gate lengths of high voltage MOSFETs in memory devices is challenging due to sub-surface leakage and punch-through issues, which increase subthreshold swing and off-state current, degrading the performance and efficiency of transistors.
Innovation Solution
A dielectric region is structured between the drain and source regions of the transistor, extending downward into the substrate to create a barrier against sub-surface conduction paths, reducing leakage current and improving the ION/IOFF ratio without degrading other electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the gate lengths of high voltage MOSFETs are shrunk to increase area efficiency, then the memory device area is reduced, but sub-surface leakage and punch-through issues increase causing degraded transistor performance
Solution Approach 1:
The patent introduces a dielectric region extending vertically downward into the substrate beneath the channel, creating a three-dimensional structure that blocks sub-surface leakage paths without increasing the lateral gate length. This vertical dimension approach allows area reduction while maintaining transistor performance by preventing punch-through effects through the added depth dimension.
Solution Approach 2:
A dielectric material is introduced as an intermediary element between the source and drain regions, extending into the substrate to block harmful sub-surface conduction paths. This intermediary dielectric region prevents direct leakage while allowing the gate length to be reduced for area efficiency.
2Area of moving object
If conventional transistor structures are used with reduced gate lengths, then area efficiency improves, but off-state current increases due to subthreshold swing degradation
Solution Approach 1:
The dielectric region extends vertically into the substrate, creating a depth-based barrier that suppresses sub-surface conduction and improves subthreshold swing characteristics without requiring increased gate length, thus maintaining area efficiency while reducing off-state current.
Solution Approach 2:
The dielectric region is locally positioned beneath the channel in the sub-surface region, providing targeted suppression of leakage paths only where needed, while leaving the rest of the transistor structure optimized for area efficiency and performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces sub-surface leakage current, enhancing the ION/IOFF ratio and subthreshold swing, thereby improving the performance and efficiency of transistors in memory devices.
Implementation Method 1
A dielectric region is structured between the drain and source regions of the transistor, extending downward into the substrate to create a barrier against sub-surface conduction paths, reducing leakage current
Data Source
AI summary
A variety of applications can include apparatus having a transistor comprising a modified channel region to address sub-surface leakage issues of the transistor. A dielectric region can be structured to extend from a channel structure of the transistor downward into the substrate for the transistor, with the dielectric region disposed between the source of the transistor and the drain of the transistor to reduce leakage current paths between the source and the drain. The dielectric region can be structured with only dielectric material or with crystalline semiconductor material surrounded by dielectric material.