Vertical MOSFET Channel Engineering for On-Resistance Reduction
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Solution Overview
Problem
Conventional vertical MOSFETs face a trade-off between reducing on-resistance (RON) and gate-drain charge (QSW), leading to increased leak current due to the short channel effect, which limits switching speed and device performance.
Innovation Solution
A semiconductor device with a highly-doped second-conductivity-type region adjacent to the second-conductivity-type base region, having a higher impurity concentration than the base region, is introduced to prevent punch-through and reduce channel length, thereby decreasing RON and QSW, and enhancing switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel length is reduced to decrease on-resistance, then the on-resistance decreases, but the short channel effect increases causing higher leak current
Solution Approach 1:
The patent applies local quality by creating a highly-doped second-conductivity-type region with higher impurity concentration than the base region. This localized doping enhancement specifically in the channel region modifies the electrical properties locally, allowing shorter channel length without excessive leak current by controlling the charge distribution and electric field in that specific area.
Solution Approach 2:
The patent changes the impurity concentration parameter by introducing a highly-doped region with higher impurity concentration than the base region. This parameter change affects the electrical characteristics of the channel, enabling reduced on-resistance while maintaining acceptable leak current levels through modified carrier concentration and mobility in the high-field region.
2Speed
If the channel length is reduced to decrease gate-drain charge, then the switching speed improves, but the punch-through effect increases
Solution Approach 1:
The highly-doped second-conductivity-type region creates local quality variation that prevents punch-through by establishing a potential barrier in the channel. The localized high impurity concentration region modifies the electric field distribution, creating a depletion barrier that stops carrier punch-through even when the channel length is reduced for faster switching.
Solution Approach 2:
The patent applies preliminary anti-action by pre-establishing the highly-doped region before operation, which creates a preventive barrier against punch-through. This pre-configured high-concentration doping region acts as a protective structure that counteracts the punch-through tendency before it can occur during device operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation effectively reduces on-resistance and gate-drain charge, preventing leak current and improving switching speed by maintaining the threshold voltage while preventing punch-through, even at shorter channel lengths.
Implementation Method 1
a second-conductivity-type region being adjacent to the second-conductivity-type base region below the first-conductivity-type source region, spaced from the gate insulating film, and having a higher impurity concentration than the second-conductivity-type base region
Implementation Method 2
forming a second-conductivity-type base region having a lower impurity concentration than the second-conductivity-type region and being adjacent to the first trench by obliquely introducing a first-conductivity-type impurity into an inner sidewall of the first trench
Data Source
AI summary
A semiconductor device includes a second-conductivity-type base region provided on a first-conductivity-type semiconductor layer, a first-conductivity-type source region provided on the second-conductivity-type base region, a gate insulating film covering an inner wall of a trench which passes through the second-conductivity-type base region and reaching the first-conductivity-type semiconductor layer, a gate electrode buried in the trench via the gate insulating film, and a second-conductivity-type region being adjacent to the second-conductivity-type base region below the first-conductivity-type source region, spaced from the gate insulating film, and having a higher impurity concentration than the second-conductivity-type base region. c≧d is satisfied, where d is a depth from an upper surface of the first-conductivity-type source region to a lower end of the gate electrode, and c is a depth from an upper surface of the first-conductivity-type source region to a lower surface of the second-conductivity-type base region.