MOSFET Channel Layout With Triangular Protrusion Near Division Regions
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved electric characteristics to maintain performance.
Innovation Solution
A semiconductor device design featuring a substrate with division regions, active patterns, and channel patterns, where the smallest width of the first active pattern is smaller than the second, and includes protruding portions on the channel patterns adjacent to the division region, enhancing the device's electric characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to reduce pattern size and design rule, then device integration density is improved, but operational properties deteriorate
Solution Approach 1:
The patent applies local quality by creating asymmetric channel patterns where only the first channel pattern (adjacent to division region) has a protruding portion, while the second channel pattern maintains a conventional rectangular shape. This localized structural modification targets specific areas experiencing short failures without altering the entire device architecture, thereby improving operational reliability in critical regions while maintaining overall device scalability.
Solution Approach 2:
The patent implements asymmetry by making the first active pattern and first channel pattern have different widths in the first direction, with the channel pattern having a protruding portion that increases its width at specific locations. This asymmetric design creates larger effective channel widths in regions prone to short failures, counteracting the effects of overall device scaling and improving operational properties without increasing the nominal pattern size.
2Reliability
If the channel pattern width is increased to improve operational properties, then electric characteristics are improved, but device area increases
Solution Approach 1:
The patent applies local quality by creating asymmetric channel patterns where only the first channel pattern (adjacent to division region) has a protruding portion, while the second channel pattern maintains a conventional rectangular shape. This localized structural modification targets specific areas experiencing short failures without altering the entire device architecture, thereby improving operational reliability in critical regions while maintaining overall device scalability.
Solution Approach 2:
The patent implements asymmetry by making the first active pattern and first channel pattern have different widths in the first direction, with the channel pattern having a protruding portion that increases its width at specific locations. This asymmetric design creates larger effective channel widths in regions prone to short failures, counteracting the effects of overall device scaling and improving operational properties without increasing the nominal pattern size.
Data Source
AI summary
A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view.