MOSFET Channel Layout With Triangular Protrusion to Prevent Shorts
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deteriorated operational properties, necessitating improved electric characteristics to maintain performance.
Innovation Solution
A semiconductor device design featuring a substrate with division regions, active patterns, and channel patterns, where the smallest width of the first active pattern is smaller than the second, and includes protruding portions on the channel patterns adjacent to the division region, enhancing the device's electric characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for small pattern size, then device density and integration are improved, but operational properties deteriorate
Solution Approach 1:
The patent applies local quality by creating asymmetric channel patterns where the first channel pattern has a different width than the second channel pattern. Specifically, the first channel pattern adjacent to the division region has a narrower width, which locally optimizes the electrical characteristics in that specific region while maintaining overall device functionality. This local variation in channel width addresses the operational property deterioration caused by overall scaling down.
Solution Approach 2:
The patent implements asymmetry by designing channel patterns with different widths - the first channel pattern has a first width and the second channel pattern has a second width that is greater than the first width. This asymmetric design creates intentional structural differences that compensate for the negative effects of scaling, particularly in regions adjacent to division regions where electrical characteristics are more sensitive to dimensional changes.
2Area of moving object
If channel patterns are made narrower to increase device density, then area utilization is improved, but short failures between source/drain and gate electrodes increase
Solution Approach 1:
The patent uses local quality by making the first channel pattern narrower than the second channel pattern in specific locations. The narrower first channel pattern is positioned adjacent to the division region where short failures are more likely to occur, providing local optimization that prevents shorts while maintaining overall high device density through the narrower channel design in critical areas.
Solution Approach 2:
The patent addresses the short failure issue by introducing dimensional variation in the channel width. Instead of uniformly scaling down all channels, the invention varies the channel width in the lateral dimension, creating a first channel pattern with width W1 and a second channel pattern with width W2 where W2 > W1. This dimensional change provides an additional degree of freedom to prevent short failures while maintaining density.
Data Source
AI summary
A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view.