Planar MOSFET Charge Induction Terminal Drift Region Resistivity
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Solution Overview
Problem
Conventional power MOSFETs face challenges with high on-state resistance and power loss due to deep body junctions, non-uniform lateral doping profiles, and thick epitaxial layers, which increase JFET resistance and gate capacitance, leading to inefficiencies in power management applications.
Innovation Solution
A planar MOSFET design featuring a charge induction terminal that induces and stores electric charges in the drift region, reducing resistivity and using a charge retention device to maintain conductivity even after the charge induction voltage is removed, with polysilicon layers embedded in an insulating oxide layer to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a large common drift region is used to reduce JFET resistance, then on-state resistance decreases, but gate capacitance increases
Solution Approach 1:
The patent changes the electrical parameters of the drift region by inducing fixed charges through ion implantation or in-situ doping. This modifies the charge distribution and conductivity profile in the drift region, allowing optimization of both on-resistance and gate capacitance by controlling the magnitude and distribution of induced charges rather than simply scaling the drift region dimensions.
Solution Approach 2:
The patent applies different doping concentrations and charge induction levels to different regions within the drift zone. By creating non-uniform charge distribution locally, the patent can reduce on-resistance in critical areas while maintaining appropriate gate capacitance characteristics, rather than uniformly increasing the entire drift region size.
2Reliability
If a thick epitaxial layer is used to sustain blocking voltage, then breakdown voltage increases, but on-resistance increases
Solution Approach 1:
The patent changes the electrical parameters of the epitaxial layer by introducing fixed charges through ion implantation or in-situ doping during growth. This modifies the conductivity profile within the thick epitaxial layer, allowing it to sustain high blocking voltages while reducing on-resistance through enhanced charge carrier concentration in the drift region.
Solution Approach 2:
The patent performs charge induction through ion implantation or in-situ doping during the epitaxial growth process itself, before device fabrication is complete. This preliminary action establishes the desired charge distribution and conductivity profile in the drift region, enabling subsequent optimization of both breakdown voltage and on-resistance without requiring additional processing steps.
3Reliability
If a long channel length is used to sustain punch-through breakdown voltage, then breakdown voltage increases, but on-resistance increases
Solution Approach 1:
The patent changes the electrical parameters along the channel by inducing fixed charges in the drift region adjacent to the channel. This modifies the electric field distribution and potential profile, allowing the channel to sustain higher punch-through breakdown voltages while maintaining lower on-resistance through improved charge carrier concentration and reduced field effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces on-resistance and power loss by improving drift region conductivity, enabling more efficient power management and potentially extending the breakdown voltage range while maintaining low power loss.
Implementation Method 1
a charge induction terminal is formed on and in contact with an insulated layer above a drift region which is defined between adjacent body regions and the charge induction terminal is to induce and store electric charge at said drift region upon application of a charge induction voltage at said charge induction terminal
Implementation Method 2
The channel of a MOSFET is typically formed by lateral diffusion of dopants underneath the polysilcon gate at a high temperature and by a long thermal cycle
Data Source
AI summary
A planar MOSFET includes a plurality of MOSFET cells. Each MOSFET cell includes an epitaxial layer of a first conductivity type, a body region of a second conductivity type inside the epitaxial layer, the second conductivity type having a polarity opposite to the first conductivity type, a source region inside the body region, a source contact portion to provide electrical contact with the source region, and a gate portion. A drift region is defined in the epitaxial layer between body regions of adjacent MOSFET cells and the gate portions of the adjacent MOSFET cells across said drift region are separated from each other with electrical insulation. A charge induction terminal is provided on the drift region to induce and store electric charge at said drift region upon application of a charge induction voltage at said charge induction terminal.