MOSFET Charge Compensation Regions for Higher Voltage Blocking

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Solution Overview

Problem

High power semiconductor switching devices face challenges in effectively blocking high voltages and maintaining high current densities due to electric field concentration at the gate oxide in the junction field effect region, which can lead to reduced voltage blocking characteristics.

Innovation Solution

The introduction of a charge compensation region formed by implanting non-activated or inert ions, such as He, Ne, or Ar, beneath the p-well region in silicon carbide MOSFETs, which helps to suppress or relieve electric field concentration and enhance voltage blocking capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If a vertical structure with thick semiconductor layer is used to block high voltages, then voltage blocking capability is improved, but electric field concentration occurs at the gate oxide in the junction field effect region

Engineering Contradiction:
Improvevoltage blocking capabilityVSAvoidelectric field concentration
Core Design Contradiction:
StrengthVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by creating a charge compensation region with specific doping characteristics at a particular location (beneath the well region) to address the local electric field concentration problem at the gate oxide interface, while maintaining the overall vertical structure for high voltage blocking

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The charge compensation region acts as an intermediary element between the well region and the drift region, compensating for excess charge and reducing electric field concentration at the critical gate oxide interface without compromising the high voltage blocking capability of the overall device structure

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If high current densities are supported in the on-state, then power handling capability is improved, but voltage blocking characteristics are reduced due to electric field concentration

Engineering Contradiction:
Improvecurrent densityVSAvoidvoltage blocking characteristics
Core Design Contradiction:
ProductivityVSStrength

Solution Approach 1:

The charge compensation region is localized beneath the well region to specifically address electric field concentration issues in the junction field effect region, allowing high current densities to be supported in the channel while maintaining voltage blocking characteristics in the drift region

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the voltage blocking characteristics of semiconductor devices by reducing electric field strength in critical areas, thereby increasing the device's ability to handle high voltages and currents.

Implementation Method 1

an implanted charge compensation region in the semiconductor layer beneath the well region

Methodology Applied
Scientific EffectCharge compensation: Coulomb's Law

Implementation Method 2

The introduction of a charge compensation region formed by implanting non-activated or inert ions, such as He, Ne, or Ar, beneath the p-well region

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS20240387620A1Mosfets with implanted charge compensation regions
Publication Date: 2024.11.21 WOLFSPEED INC
  • US20240387620A1 patent drawing
  • US20240387620A1 patent drawing
  • US20240387620A1 patent drawing

AI summary

A semiconductor device includes a semiconductor layer having a first conductivity type, a well region in the semiconductor layer, the well region having a second conductivity type opposite the first conductivity type, a source region having the first conductivity type in the well region, and an implanted charge compensation region in the semiconductor layer beneath the well region. The source region is adjacent a channel region in the well region. A method of forming a semiconductor device includes forming a well region having a second conductivity type in a semiconductor layer having a first conductivity type opposite the second conductivity type, forming a source region having the first conductivity type in the well region, and implanting ions into the semiconductor layer to form a charge compensation region in the semiconductor layer beneath the well region. The source region is adjacent a channel region in the well region.