Non-Overlapping MOSFET Clock Circuit Without Extra Delay Margins
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Solution Overview
Problem
Existing clock signal circuits for switched capacitor circuits face challenges in generating non-overlapping output clock signals due to unpredictable delays and dependencies on process, supply voltage, and temperature, which require additional time margins, hindering the implementation of fast switched capacitor circuits.
Innovation Solution
A clock signal circuit comprising PMOSFETs and NMOSFETs is designed to generate non-overlapping output clock signals without the need for extra delay, ensuring that switches are only closed when the other is open, using specific configurations and connections of transistors to prevent overlap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delays and logic gates are incorporated in the two phase clock signal path to prevent switch overlap, then switch closure overlap is prevented, but circuit speed is reduced due to extra time margins
Solution Approach 1:
The patent introduces intermediate control nodes (first and second intermediate control nodes) that mediate between the clock signal and the switch gate signals. These intermediaries process the clock signal to generate non-overlapping control signals for phase 1 and phase 2 switches, eliminating the need for conservative time margins while ensuring proper switch timing.
Solution Approach 2:
The circuit performs preliminary action by generating the non-overlapping clock signals in advance through the intermediate control nodes before the switches need to operate. The intermediate nodes prepare the control signals with proper timing relationships, so that when the switches are activated, they are already synchronized without requiring extra delay margins.
2Reliability
If delays are added to accommodate unpredictable propagation times, then switch overlap is prevented in extreme situations, but the extra time margin reduces circuit performance
Solution Approach 1:
The intermediate control nodes act as mediators that actively manage the timing relationships between clock phases. Instead of adding passive delay margins, the intermediaries dynamically generate control signals with precise timing, ensuring reliable switch operation without sacrificing time performance.
Solution Approach 2:
The circuit changes the timing parameters of the clock signals through the intermediate control nodes. By actively adjusting the phase and timing relationships in the intermediate stage, the circuit achieves reliable switch control with optimized time margins rather than using conservative fixed delays.
3Reliability
If conservative time margins are included to account for process, supply voltage and temperature dependence, then switch overlap is prevented, but fast switched capacitor circuit implementation is hindered
Solution Approach 1:
The intermediate control nodes serve as adaptive mediators that compensate for process, voltage, and temperature variations. By processing the clock signal through these intermediaries, the circuit maintains reliable switch timing across varying conditions without requiring conservative time margins that would limit speed performance.
Solution Approach 2:
The intermediate control nodes provide dynamic timing adjustment that adapts to varying operating conditions. Rather than using fixed conservative margins, the intermediate stage actively manages timing relationships to maintain reliability while enabling faster operation across different process, voltage, and temperature conditions.
Data Source
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AI summary
The disclosure relates to clock signal circuits for generating non-overlapping output clock signals. Example embodiments include a clock signal circuit (100) for generating first and second non-overlapping output clock signals (ϕ1p, ϕ2n), the clock signal circuit (100) comprising: first and second PMOSFETs (M1, M3); first and second NMOSFETs (M2, M4); a clock signal input node (101) connected to a gate of the first PMOSFET (M1) and a gate of the second NMOSFET (M4); a first voltage rail (102) connected to a source of the first PMOSFET (M1); a second voltage rail (103) connected to a source of the second NMOSFET (M4); a first clock signal output node (104) connected to a drain of the first PMOSFET (M1), a drain of the first NMOSFET (M2) and a source of the second PMOSFET (M3); and a second clock signal output node (105) connected to a drain of the second PMOSFET (M3), a source of the first NMOSFET (M2) and a drain of the second NMOSFET (M4).