MOSFET Clock Phase Circuit for Non-Overlapping Switching
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Solution Overview
Problem
Existing clock signal circuits require additional delay margins to prevent switch overlap, which is sub-optimal for fast switched capacitor circuits due to unpredictable process, supply voltage, and temperature dependencies.
Innovation Solution
A clock signal circuit design using PMOSFETs and NMOSFETs with specific connections to generate non-overlapping output clock signals, eliminating the need for extra delay by ensuring switches are only activated when their counterparts are deactivated.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delays and logic gates are incorporated in the two phase clock signal path to prevent switch overlap, then switch closure safety is improved, but circuit complexity and propagation time increase
Solution Approach 1:
The patent introduces an intermediary circuit comprising a first PMOSFET, first NMOSFET, second PMOSFET, and second NMOSFET that acts as a mediator between the clock signal source and the switching transistors. This intermediary circuit generates the two non-overlapping clock phases through its internal transistor switching mechanism, eliminating the need for external delay elements and logic gates while ensuring reliable non-overlapping switch closure.
2Reliability
If extra time margin is included between phase 1 and phase 2 switch closures to prevent overlap, then switch overlap prevention is improved, but switching speed decreases
Solution Approach 1:
The patent implements preliminary action by designing the intermediary circuit to proactively generate non-overlapping clock phases before they are needed by the switching transistors. The circuit internally ensures that one phase is already deactivated before the other phase activates, eliminating the need for conservative time margins and enabling faster switching speeds without risking switch overlap.
3Reliability
If delays are added to accommodate unpredictable propagation times, then clock signal reliability is improved, but time efficiency deteriorates
Solution Approach 1:
The patent applies parameter changes by utilizing the inherent electrical characteristics of PMOSFETs and NMOSFETs to dynamically control the timing parameters of the clock phases. The circuit leverages the different switching speeds and voltage characteristics of PMOS and NMOS transistors to automatically adjust the phase timing, ensuring reliable non-overlapping operation without adding fixed delay margins that would reduce time efficiency.
Data Source
AI summary
The disclosure relates to clock signal circuits for generating non-overlapping output clock signals. Example embodiments include a clock signal circuit (100) for generating first and second non-overlapping output clock signals (φ1p, φ2n), the clock signal circuit (100) comprising: first and second PMOSFETs (M1, M3); first and second NMOSFETs (M2, M4); a clock signal input node (101) connected to a gate of the first PMOSFET (M1) and a gate of the second NMOSFET (M4); a first voltage rail (102) connected to a source of the first PMOSFET (M1); a second voltage rail (103) connected to a source of the second NMOSFET (M4); a first clock signal output node (104) connected to a drain of the first PMOSFET (M1), a drain of the first NMOSFET (M2) and a source of the second PMOSFET (M3); and a second clock signal output node (105) connected to a drain of the second PMOSFET (M3), a source of the first NMOSFET (M2) and a drain of the second NMOSFET (M4).