MOSFET Layout Common Source Body for Integration
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Solution Overview
Problem
Conventional MOSFET layouts face challenges in achieving higher integration and smaller layout area while maintaining electrostatic discharge (ESD) protection, as increasing gate width to enhance current density leads to larger layout areas and lower integration.
Innovation Solution
The MOSFET layout design includes a gate region outside the drain region, with a source region and body region having multiple sections and portions that share common areas, optimizing the layout to reduce area usage and enhance integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the effective width of the gate is increased to raise current density, then the current density is improved, but the layout area becomes bigger and integration becomes lower
Solution Approach 1:
The patent merges the body regions of two neighboring MOSFETs into a shared common body region. Instead of each MOSFET having its own separate body region, the invention combines them so that one body region serves both devices, thereby reducing the total layout area while maintaining the required current density and ESD protection capabilities
Solution Approach 2:
The common body region performs multiple functions: it serves as the body region for both neighboring MOSFETs simultaneously and provides ESD protection for both devices. This multi-functional design allows the structure to maintain reliability requirements while minimizing the occupied area
2Reliability
If the drain region width is increased to sustain high-voltage for ESD protection, then the ESD protection capacity is improved, but the layout area becomes bigger and integration becomes lower
Solution Approach 1:
The patent combines the ESD protection function for two neighboring MOSFETs into a single common drain region. This shared drain region sustains the high-voltage ESD stress for both devices simultaneously, eliminating the need for separate wide drain regions for each MOSFET and thereby reducing the total layout area while maintaining adequate ESD protection
Data Source
AI summary
A MOSFET layout is disclosed. The MOSFET comprises a drain region, a gate region, a source region and a body region. The gate region is disposed outside the drain region and adjacent to the drain region. The source region has a plurality of source sections, which are disposed outside of the gate region and adjacent to the gate region. Each of two adjacent source sections has a source blank zone there between. The body region has at least two body portions, which are disposed at the source blank zones and adjacent to the gate region.