MOSFET Contact Region Layout for Parasitic Bipolar Suppression

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Solution Overview

Problem

Semiconductor devices, such as MOSFETs, experience characteristic fluctuations due to parasitic bipolar transistor operation, leading to unreliable performance and breakdown issues, primarily caused by potential differences between the p-type base region and the n+-type source region.

Innovation Solution

The semiconductor device incorporates a p+-type contact region with a higher impurity concentration than the p-type base region, separated from the p+-type contact region, to reduce the potential difference and suppress parasitic bipolar transistor operation, while maintaining the p+-type contact region's position under the n+-type source region to minimize impurity diffusion and voltage threshold fluctuations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a p+-type contact region is formed to reduce potential difference and suppress parasitic bipolar transistor operation, then reliability is improved, but device complexity increases due to additional impurity concentration gradients and region separations

Engineering Contradiction:
ImprovereliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by creating a p+-type contact region with higher impurity concentration specifically at the contact area, while maintaining lower impurity concentration in the base region. This localized impurity concentration gradient reduces potential difference and suppresses parasitic bipolar transistor operation, thereby improving reliability without requiring uniform changes throughout the entire device structure.

Inventive Principle:
Principle #3Local quality

2Reliability

If the p+-type contact region is separated from the p+-type contact region, then parasitic bipolar transistor operation is suppressed, but manufacturing precision requirements increase to maintain proper positioning and impurity concentration gradients

Engineering Contradiction:
Improveparasitic bipolar transistor suppressionVSAvoidmanufacturing precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent segments the contact structure into distinct regions: a p+-type contact region with high impurity concentration and a p-type base region with lower impurity concentration. This segmentation creates physical and electrical separation that suppresses parasitic bipolar transistor operation. The segmented structure allows for controlled impurity diffusion boundaries, managing manufacturing precision requirements through defined region interfaces.

Inventive Principle:
Principle #1Segmentation

3Reliability

If impurity concentration in the contact region is increased to reduce electrical resistance, then on-resistance is reduced, but impurity diffusion to the gate increases causing voltage threshold fluctuations

Engineering Contradiction:
Improveelectrical resistance controlVSAvoidvoltage threshold control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the impurity concentration parameter locally by creating a p+-type contact region with higher impurity concentration than the base region. This parameter change reduces electrical resistance in the contact area. The localized nature of this parameter change, confined to the contact region rather than the entire device, limits impurity diffusion to the gate, thereby controlling voltage threshold fluctuations while achieving low on-resistance.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240096962A1Semiconductor device and method for the same
Publication Date: 2024.03.21 KK TOSHIBA
  • US20240096962A1 patent drawing
  • US20240096962A1 patent drawing
  • US20240096962A1 patent drawing

AI summary

According to one embodiment, a semiconductor device includes a first electrode, first to fourth semiconductor regions, a gate electrode, and a second electrode. The third semiconductor region is located on a portion of the second semiconductor region. The fourth semiconductor region includes a first portion positioned on the third semiconductor region and a second portion arranged with the first portion in a second direction. A first-conductivity-type impurity concentration of the first portion is less than a first-conductivity-type impurity concentration of the second portion. The gate electrode faces the second semiconductor region via a gate insulating layer in the second direction. The second electrode is located on the second and fourth semiconductor regions. The second electrode contacts the first and second portions. The second electrode includes a connection part that contacts the third semiconductor region and the portion of the second semiconductor region in the second direction.