Semiconductor Package with Interleaved MOSFETs and Control Circuit
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Solution Overview
Problem
The existing semiconductor devices for high-side and low-side switches in inverter circuits face challenges in improving performance and wiring design flexibility, particularly when mounted on control boards for 6-phase or 12-phase BLDC motors, due to restrictive wiring requirements and thermal interference between high and low-side MOSFETs.
Innovation Solution
A semiconductor device package integrating a high-side MOSFET, a low-side MOSFET, and a control circuit, where the control circuit is positioned between the high and low-side MOSFETs to reduce thermal interference and enhance packaging efficiency, with leads arranged to facilitate series connection and efficient wiring on the control board.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the control circuit is positioned between the high and low-side MOSFETs, then thermal interference is reduced, but device complexity increases
Solution Approach 1:
The patent divides the semiconductor device into separate functional modules: high-side MOSFET chip, low-side MOSFET chip, and control circuit chip, each mounted on separate die pads. This segmentation allows independent thermal management and positioning, reducing thermal interference between the power MOSFETs and control circuit while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
The patent arranges the high-side and low-side MOSFETs on opposite sides of the control circuit in a planar configuration, utilizing spatial dimensionality to separate thermal zones. The control circuit is positioned on the die pad between the two MOSFET die pads, creating distinct thermal pathways and reducing heat coupling between components.
2Adaptability or versatility
If leads are arranged to intersect with sealing body sides, then wiring design flexibility is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from traditional planar lead arrangements to a three-dimensional configuration where leads extend from die pads on opposite sides of the sealing body and intersect with the side surfaces. This spatial arrangement provides flexible wiring options for external connections while the intersecting geometry establishes clear manufacturing targets for lead positioning and attachment.
Solution Approach 2:
The lead arrangement is pre-configured during package assembly, with leads attached to die pads before final sealing. This preliminary positioning ensures that the intersecting lead configuration is established with appropriate precision during the assembly process, rather than requiring post-assembly adjustments.
Data Source
AI summary
The semiconductor device of the present invention is a semiconductor device in which a first semiconductor chip including a first field effect transistor for a high-side switch, a second semiconductor chip including a second field effect transistor for a low-side switch, and a third semiconductor chip including a circuit that controls each of the first and second semiconductor chips are sealed with a sealing portion. A lead electrically connected to a pad of the first semiconductor chip for a source of the first field effect transistor and a lead electrically connected to a back-surface electrode of the second semiconductor chip for a drain of the second field effect transistor are disposed on the same side of the sealing portion in a plan view.