Counter-Doping Noise Reduction in MOSFET Substrate
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Solution Overview
Problem
Flicker noise in MOSFET devices, particularly in battery-driven and RF circuits, is a significant issue as it degrades performance and increases power consumption, and existing methods fail to effectively reduce noise without compromising power efficiency or chip area.
Innovation Solution
The use of counter-doping techniques involving compound dopants containing noise-reducing species like fluorine, chlorine, and deuterium, integrated into various processing steps of semiconductor fabrication, to reduce flicker noise by increasing the concentration of noise-reducing ions within the substrate without additional implantation steps, thereby minimizing crystal damage and dopant segregation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional doping methods are used to reduce flicker noise, then noise reduction is achieved, but additional implantation steps are required increasing process complexity and crystal damage
Solution Approach 1:
The patent combines noise-reducing dopant introduction with existing counter-doping processing steps. Instead of adding separate implantation steps, the method integrates noise reduction functionality into the counter-doping process that is already required for threshold voltage control and short-channel effect mitigation, thereby reducing process complexity while achieving noise reduction
Solution Approach 2:
The patent introduces noise-reducing dopants during the counter-doping step that occurs before gate insulator formation. This preliminary action ensures that the noise-reducing dopants are positioned in the substrate before the gate insulator is formed, allowing them to effectively passivate interface traps and reduce flicker noise without requiring additional subsequent implantation steps
2Object-affected harmful factors
If additional implantation steps are added to reduce flicker noise, then noise reduction is achieved, but power consumption and chip area increase
Solution Approach 1:
The patent merges noise reduction with existing counter-doping steps, eliminating the need for additional implantation cycles. By combining multiple functions (threshold voltage control, short-channel effect mitigation, and noise reduction) into a single processing step, the method reduces overall process time and power consumption while achieving comprehensive device optimization
3Object-affected harmful factors
If high concentration of noise-reducing dopants is introduced, then flicker noise is reduced, but dopant segregation and crystal damage increase
Solution Approach 1:
The patent introduces noise-reducing dopants at specific locations in the substrate where counter-doping is performed, rather than uniformly throughout the entire substrate. This localized approach concentrates the noise-reducing effect at the interface region where it is most needed while minimizing overall dopant concentration, thereby reducing the risk of dopant segregation and crystal damage in other regions
Solution Approach 2:
The patent utilizes the counter-doping process to deliver noise-reducing dopants at controlled concentrations and depths. By leveraging the established counter-doping parameters (dose, energy, profile) and adding noise-reducing dopant introduction to this existing process, the method achieves precise control over dopant distribution, preventing excessive concentration that would lead to segregation while ensuring sufficient noise reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces flicker noise in MOSFET devices, improving the signal-to-noise ratio and power efficiency while maintaining chip area efficiency, by distributing noise-reducing dopants throughout the substrate, thus enhancing the overall performance of switching and non-switching circuits.
Implementation Method 1
distributing noise-reducing dopants throughout the substrate
Data Source
AI summary
One or more embodiments describe a method of fabricating a silicon based metal oxide semiconductor device, including introducing a first dopant into a first partial completion of the device, the first dopant including a first noise reducing species; and introducing a second dopant into a second partial completion of the device, the second dopant and the first dopant being opposite conductivity types.