MOSFET Current Limiter for Squib Driver Stability

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Solution Overview

Problem

Conventional squib driver circuits face instability and high costs due to complex pole-zero compensation networks and potential oscillations, especially in unpowered states and when dealing with wide ranges of resistive, inductive, or capacitive loads, leading to undesired squib deployment.

Innovation Solution

An electronic device with a first MOS transistor coupled to a common gate node, a second MOS transistor with a reference current controlled by a control loop, and a diode to ensure stable current limiting even in unpowered states, using a resistive divider and diode to manage power supply levels and prevent inadvertent activation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional current limiter with pole-zero compensation network is used, then current limiting capability is achieved, but device complexity and cost increase while stability remains problematic

Engineering Contradiction:
ImprovestabilityVSAvoidcompensation network complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent removes the complex pole-zero compensation network (resistors RZ, RZ1, capacitors CC, CC1) from the circuit while maintaining stability. The solution extracts only the essential current limiting function using simpler components, eliminating unnecessary complexity that previously caused instability and high costs.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of adding compensation networks to stabilize the circuit, the patent inverts the approach by using a simpler circuit topology that inherently provides stability. The current limiter uses a direct comparison of voltages across sense resistors without requiring complex frequency compensation, achieving stability through fundamental circuit principles rather than additive compensation stages.

Inventive Principle:
Principle #13The other way round (Inversion)

2Reliability

If Miller capacitance discharge path is not provided in unpowered state, then circuit simplicity is maintained, but inadvertent squib deployment occurs due to charge accumulation

Engineering Contradiction:
Improvesquad deployment preventionVSAvoiddischarge path complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a discharge path that is always present but only becomes active when needed. The resistor R7 connected to the common gate node provides a continuous discharge path that prevents charge accumulation from Miller capacitance, ensuring the circuit is ready for safe operation without requiring complex conditional switching mechanisms.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If surge current limiter is used to limit energy in squib, then fault protection is improved, but device complexity and area increase

Engineering Contradiction:
Improvefault protectionVSAvoidIC area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the current limiting function and surge protection function into a single integrated circuit without requiring separate surge current limiter components. The current limiter circuit inherently provides surge protection by limiting the maximum current through the squib, eliminating the need for additional protective circuitry and reducing overall IC area.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8553388B2Electronic device for controlling a current
Publication Date: 2013.10.08 TEXAS INSTRUMENTS INC
  • US8553388B2 patent drawing
  • US8553388B2 patent drawing
  • US8553388B2 patent drawing

AI summary

An electronic device is provided for controlling a current. The electronic device includes a first MOS transistor coupled with a gate to a common gate node, with a source to ground and with a drain to a pin so as to receive from the pin a current to be controlled. There is a second MOS transistor coupled with a gate to the common gate node, with a source to ground and with a drain so as to receive a reference current controlled by a control loop. There is a first resistor coupled between the common gate node and ground.