Power MOSFET Deep Source Contact Trench Segmentation
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Solution Overview
Problem
Current power MOSFET technologies face challenges in achieving optimal breakdown voltage and on-state resistance due to the trade-off between device breakdown voltage and on-state resistance, particularly in the design of deep source contact trenches, which leads to inefficiencies and yield reductions in semiconductor device fabrication.
Innovation Solution
The implementation of innovative SCT layout design enhancements, including restricting the length of deep source contact trenches to linear portions of polysilicon gates and aligning them to complementary curvilinear geometries, ensures uniform processing and reduces parasitic resistance, thereby improving yield and operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the deep source contact trench is extended deeper into the substrate to reduce on-state resistance, then the on-state resistance decreases, but the manufacturing precision and yield deteriorate due to processing difficulties
Solution Approach 1:
The source contact region is segmented into multiple discrete trenches rather than one continuous deep trench. This segmentation allows each individual trench to be processed with better control and uniformity, while collectively they provide the necessary low resistance path. The segmentation principle resolves the contradiction by dividing the problematic deep continuous structure into manageable units that are easier to manufacture precisely.
Solution Approach 2:
The solution transitions from a single deep vertical trench to multiple shallower trenches arranged in a specific pattern. By distributing the contact function across multiple dimensions (spacing multiple trenches apart), the design achieves equivalent or better electrical performance while maintaining manufacturability. This dimensional redistribution eliminates the need for excessively deep single trenches that are difficult to process uniformly.
2Loss of energy
If the SCT trench length is increased to improve electrical connection, then the parasitic resistance decreases, but the device complexity and fabrication difficulty increase
Solution Approach 1:
The single long SCT trench is segmented into multiple shorter trenches. Each shorter trench is easier to fabricate with consistent dimensions, reducing the complexity of the etching and filling processes. The segmented approach maintains low parasitic resistance through parallel conduction paths while avoiding the fabrication challenges of single ultra-deep trenches.
Solution Approach 2:
Rather than creating one excessively deep trench that pushes the limits of fabrication capability, the design uses multiple trenches that extend partially to the substrate but not as deeply. This partial action in multiple locations achieves the same electrical effect with less extreme individual features, simplifying the overall fabrication process.
3Reliability
If deeper SCT trenches are fabricated to reduce contact resistance, then the electrical performance improves, but the yield and manufacturing precision deteriorate due to non-uniform processing
Solution Approach 1:
The contact function is distributed across multiple segmented trenches rather than relying on a single deep trench. This segmentation provides redundancy and reduces the impact of any single trench processing variation, thereby maintaining high yield while achieving the desired electrical performance. The segmented structure is more tolerant to manufacturing variations.
Solution Approach 2:
The design applies the source contact function locally at multiple discrete positions rather than through one continuous deep structure. Each local trench can be optimized for uniform processing, and the collective arrangement achieves the required electrical performance. This local quality approach improves both yield and electrical characteristics.
Data Source
AI summary
A method of forming an electronic device includes forming a plurality of closed loops over a semiconductor substrate. Each closed loop has a first and a second polysilicon gate structure joined at first and second ends. Each closed loop includes an inner portion and an end portion. In the inner portion the first polysilicon gate structure runs about parallel to the second polysilicon gate structure. In the outer portion the first polysilicon gate structure converges with the second polysilicon gate structure. The method further includes forming a plurality of trench contacts. Each of the trench contacts is located between a respective pair of closed loops, passes through an epitaxial layer and contacts the substrate. The length of the trench contacts is no greater than the length of the inner portions.