Delta Channel Width Extraction for Nano-Scale MOSFETs
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Solution Overview
Problem
Conventional methods for extracting delta channel width in nano-scale MOSFETs are inaccurate due to reliance on I-V characteristics, requiring multiple iterations and additional devices, and fail to account for STI stress and parasitic resistances, leading to errors in effective channel width determination.
Innovation Solution
A parameter extraction method using high-frequency test apparatuses and three-dimensional capacitance simulations to calculate delta channel width by measuring gate capacitances, intrinsic gate capacitances, and fringing capacitances between gate fingers and active regions, allowing for precise determination of effective channel width without additional reference devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional I-V based method is used for delta channel width extraction, then the extraction process can be performed, but multiple iterations are required and additional errors are introduced due to STI stress and parasitic resistances
Solution Approach 1:
The patent replaces the conventional I-V based extraction method with a high-frequency capacitance-based method. By measuring gate capacitance (Cgg) at high frequencies and using the relationship between capacitance and channel width, the method avoids the iterative process and errors associated with I-V measurements, particularly those caused by STI stress and parasitic resistances.
Solution Approach 2:
The patent changes the measurement parameter from current-voltage characteristics to high-frequency capacitance characteristics. By measuring Cgg at different frequencies and using the frequency-dependent capacitance behavior, the method directly extracts delta channel width without requiring multiple iterations or additional reference devices.
2Measurement precision
If conventional I-V based method is used, then delta channel width can be extracted, but a very wide MOSFET is needed as reference device which increases device area
Solution Approach 1:
The patent extracts the delta channel width information directly from the high-frequency capacitance measurements of the actual device without requiring a separate wide MOSFET reference device. The method separates the delta width extraction from the need for reference devices by utilizing the frequency-dependent capacitance characteristics of the gate.
3Measurement precision
If conventional I-V based method is used for short channel devices, then delta channel width can be extracted, but source/drain parasitic resistances dominate and introduce additional errors
Solution Approach 1:
The patent replaces the I-V measurement approach with high-frequency capacitance measurement, which is not affected by source/drain parasitic resistances. The capacitance-based method directly probes the channel properties without being dominated by the parasitic resistances that plague I-V measurements in short channel devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method provides a simple and precise extraction of delta and effective channel widths, improving accuracy and reducing errors associated with STI stress and parasitic resistances, applicable to nano-scale MOSFETs and extending to next-generation 3D techniques.
Implementation Method 1
providing a high-frequency test apparatus for measuring the first multi-finger device to get a first gate capacitance, and for measuring the second multi-finger device to get a second gate capacitance
Implementation Method 2
performing a three-dimensional capacitance simulation for respectively computing the capacitances between the sidewall of the gate fingers and the active region of the source and between the sidewall of the gate fingers and the active region of the drain to get a first gate sidewall fringing capacitance
Data Source
AI summary
A parameter extraction method for semiconductor devices includes: providing a first multi-finger device and a second multi-finger device, wherein the gate-finger numbers between the first and second multi-finger devices are different; performing an open de-embedding, then the high-frequency test apparatus measuring a first intrinsic gate capacitance of the first multi-finger device and a second intrinsic gate capacitance of the second multi-finger device; calculating a slope according to the first and second intrinsic gate capacitances, and the first and second gate-finger numbers; performing a 3D capacitance simulation for computing the poly finger-end fringing capacitances; utilizing a long channel device for measuring the gate capacitance and extracting the intrinsic gate capacitance, then calculating an inversion channel capacitance per unit area; and computing a delta channel width of the semiconductor device, according to the slope, the poly finger-end fringing capacitance, and the inversion channel capacitance per unit area.