MOSFET Dislocation Planes for Drive Current
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Solution Overview
Problem
Current techniques for enhancing carrier mobility in metal-oxide-semiconductor (MOS) devices, specifically in n-type and p-type MOS devices, are inadequate in consistently inducing desired tensile and compressive stresses in the channel regions to improve performance.
Innovation Solution
The method involves forming dislocation planes through pre-amorphization implantation and subsequent annealing steps to create strained capping layers that apply tensile stress to the channel region of MOSFETs, with multiple dislocation planes increasing stress levels, and silicidation to enhance drive current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple dislocation planes are formed in the source/drain regions, then channel stress is increased and drive current is improved, but device complexity and manufacturing process complexity increase
Solution Approach 1:
The source/drain regions are segmented into multiple discrete dislocation planes rather than a single continuous structure. Each dislocation plane is formed through separate implantation and annealing steps, allowing independent control and optimization of stress distribution across different depth levels or lateral positions in the channel region.
Solution Approach 2:
Different dislocation planes are positioned at specific locations within the source/drain regions to create non-uniform stress distribution. This allows targeted stress application in regions where it most benefits carrier mobility while avoiding stress in regions where it could be detrimental, achieving local optimization of device performance.
2Manufacturing precision
If multiple dislocation planes are formed through separate implantation and annealing steps, then manufacturing precision is improved for stress control, but ease of manufacture deteriorates
Solution Approach 1:
Offset spacers are formed prior to the dislocation plane formation process to pre-establish the lateral positioning for subsequent implantation steps. This preliminary structuring ensures precise alignment and spacing of multiple dislocation planes without requiring complex real-time adjustment mechanisms during the implantation and annealing processes.
Solution Approach 2:
The implantation conditions (energy, dose, angle) and annealing parameters (temperature, time, atmosphere) are systematically varied for each dislocation plane formation step to achieve the desired stress magnitude and distribution. By controlling these parameters, precise stress engineering is achieved while maintaining compatibility with existing CMOS fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases channel stress, improving drive current in MOSFETs by optimizing stress distribution and recrystallization, leading to enhanced performance in MOS devices.
Implementation Method 1
performing a first annealing to the first strained capping layer and the first PAI region to form a first dislocation plane in a semiconductor region adjacent to the gate electrode
Implementation Method 2
forming dislocation planes through pre-amorphization implantation and subsequent annealing steps to create strained capping layers
Implementation Method 3
induce a tensile stress in the channel region of an n-type MOS device in a source-to-drain direction, and to induce a compressive stress in the channel region of a p-type MOS device
Data Source
AI summary
A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET), which includes forming a first dislocation plane adjacent to a gate electrode of the MOSFET, and forming a second dislocation plane adjacent to the gate electrode of the MOSFET. The first and the second dislocation planes are on a same side of the gate electrode, and extend into source/drain regions of the MOSFET.