MOSFET Threshold Voltage Matching via Controlled Dopant Diffusion

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Solution Overview

Problem

Manufacturing process variations lead to random dopant fluctuation in MOSFET devices, causing mismatched threshold voltages between transistors, which affects the reliability and performance of semiconductor integrated circuits.

Innovation Solution

A manufacturing method involving the formation of shallow trench isolation regions, dielectric layers, conductive layers, and lightly doped source/drain regions, along with rapid thermal anneal processes, to control doping concentrations and diffusion depths, ensuring consistent transistor characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If LDD structure is formed to mitigate hot carriers injection, then reliability of MOSFET device is improved, but random dopant fluctuation causes threshold voltage mismatch

Engineering Contradiction:
ImproveMOSFET device reliabilityVSAvoidthreshold voltage matching
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent employs multiple annealing processes (rapid thermal anneal, laser anneal, flash anneal) with different temperature profiles and durations to precisely control dopant distribution. By changing the thermal processing parameters, the invention achieves both the desired LDD structure for reliability and reduced dopant fluctuation for threshold voltage matching.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent performs preliminary dopant implantation to form the LDD structure before final threshold adjustment. This preliminary action establishes the base dopant distribution that provides hot carrier mitigation, while subsequent annealing processes refine the distribution to reduce threshold voltage mismatch.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If doping concentration is increased to improve transistor characteristics, then device performance is improved, but dopant diffusion increases causing threshold voltage variation

Engineering Contradiction:
Improvetransistor performanceVSAvoidthreshold voltage consistency
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent employs periodic thermal processing with multiple distinct annealing steps rather than continuous heating. Each annealing pulse is carefully controlled in duration and temperature to achieve dopant redistribution without excessive diffusion, maintaining both performance and threshold voltage consistency.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent utilizes rapid phase transitions in thermal processing (rapid heating and cooling cycles) to control dopant behavior. The quick thermal cycles allow dopant redistribution at elevated temperatures followed by rapid quenching that freezes the desired dopant distribution, preventing excessive diffusion.

Inventive Principle:
Principle #36Phase transitions

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method reduces random dopant fluctuation, minimizing threshold voltage mismatches and enhancing the reliability and performance of semiconductor devices by stabilizing the properties of MOSFETs.

Implementation Method 1

rapid thermal anneal processes

Methodology Applied
Scientific EffectRapid thermal anneal: Heating

Implementation Method 2

diffusion depths

Methodology Applied
Scientific EffectDopant diffusion: Diffusion

Data Source

PatentUS10971404B2Semiconductor device
Publication Date: 2021.04.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10971404B2 patent drawing
  • US10971404B2 patent drawing
  • US10971404B2 patent drawing

AI summary

A semiconductor device includes a semiconductor substrate, and a first transistor. The first transistor has a first gate on the semiconductor substrate, and a first lightly doped source/drain region within the semiconductor substrate to determine a first channel region beneath the first gate. A doping ratio determined as a concentration of the first lightly doped source/drain region divided by a concentration of the first channel region ranges from 1.0×1013 to 1.0×1017.