Power MOSFET Drift Layer Doping for Low Rdson and Breakdown Voltage

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Solution Overview

Problem

Existing technologies face challenges in improving the on-resistance (Rdson) of high voltage DMOS-type Silicon and Silicon Carbide Power MOSFET devices without degrading the breakdown voltage.

Innovation Solution

A wafer fabrication process involving multiple thermal drive processes and dopant concentration gradients is employed to form a transistor structure with specific dopant concentrations and layers, including a drift layer, body layer, and source layer, to enhance on-resistance while maintaining breakdown voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If conventional fabrication processes are used to reduce on-resistance, then Rdson decreases, but breakdown voltage degrades

Engineering Contradiction:
Improveon-resistanceVSAvoidbreakdown voltage
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The drift layer is segmented into multiple regions with different dopant concentrations (first drift region with lower concentration, second drift region with higher concentration). This segmentation allows the lower concentration region to reduce on-resistance while the higher concentration region maintains breakdown voltage, resolving the contradiction between these two parameters.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the drift layer are assigned different dopant concentrations tailored to their specific functional requirements. The first drift region has optimized low concentration for minimal resistance, while the second drift region has higher concentration for voltage sustainment, applying local quality to resolve the global contradiction.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If multiple thermal drive processes are performed, then dopant concentration gradients are optimized, but manufacturing complexity increases

Engineering Contradiction:
Improvedopant concentration gradientVSAvoidnumber of thermal drive processes
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Dopant layers are pre-positioned at specific depths during implantation before thermal drive processes. The first dopant layer is implanted at a first depth and the second dopant layer at a second depth, establishing the concentration gradient structure in advance. This preliminary action reduces the complexity of subsequent thermal processing by pre-defining the dopant distribution architecture.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The multiple thermal drive processes automatically diffuse dopants from their implanted positions to create the desired concentration gradients. The diffusion process itself, driven by temperature, self-organizes the dopant distribution based on the initial layered structure, reducing the need for additional complex processing steps to achieve the gradient.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The process effectively reduces on-resistance without compromising breakdown voltage, enhancing the performance of the transistor.

Implementation Method 1

performing a first thermal drive process after implanting the body layer, implanting a source layer within an upper portion of the body layer, performing a second thermal drive process after implanting the source layer, implanting a second JFET layer within a portion of the drift layer, performing a third thermal drive process after implanting the second JFET layer

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 2

implanting a first JFET layer within a portion of the drift layer, implanting a body layer within a portion of the drift layer, implanting a source layer within an upper portion of the body layer, implanting a second JFET layer within a portion of the drift layer

Methodology Applied
Scientific EffectIon Implantation: Ion Implantation

Data Source

PatentUS20250294824A1Transistor and method for manufacturing same
Publication Date: 2025.09.18 MICROCHIP TECHNOLOGY INC
  • US20250294824A1 patent drawing
  • US20250294824A1 patent drawing

AI summary

A transistor that may include a substrate. A drift layer within the substrate. A first JFET layer within a portion of the drift layer. A body layer within a portion of the drift layer. A source layer within an upper portion of the body layer. A second JFET layer within a portion of the drift layer. An insulating layer over a portion of the source layer. A gate electrode over the insulating layer.