MOSFET Electrode SONO Coating for Gate Charge Reduction
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Solution Overview
Problem
Conventional MOSFETs face challenges with high total gate charge and figure of merit (FOM), which affect switching speed and efficiency, particularly due to the dimple structure in their manufacturing process.
Innovation Solution
A field effect transistor with an electrode coated sequentially by an oxide layer and a nitride layer is manufactured, forming a surrounding-oxide and surrounding-nitride layer structure to reduce total gate charge and FOM, achieved through specific steps including epitaxial layer formation, trench etching, and layer deposition and removal processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a dimple structure is formed in the gate during conventional MOSFET manufacturing, then the manufacturing process is completed, but the total gate charge and figure of merit increase, reducing switching speed and efficiency
Solution Approach 1:
The patent removes the harmful dimple structure from the gate by selectively etching away the oxide and nitride layers in the trench region, extracting the problematic geometric feature that causes increased gate charge while maintaining the beneficial surrounding oxide-nitride-oxide (SONO) structure for manufacturing ease
Solution Approach 2:
The patent applies different structures to different regions: the SONO structure is maintained in the field region for manufacturing simplicity, while the trench region is locally modified by removing the dimple structure through selective etching, creating a non-uniform gate structure with different properties in different zones to optimize both manufacturing and performance
2Ease of manufacture
If a dimple structure is formed in the gate during conventional MOSFET manufacturing, then the manufacturing process is completed, but the figure of merit increases, reducing switching efficiency
Solution Approach 1:
The patent extracts the harmful dimple structure from the gate by selective etching in the trench region, removing the geometric feature that increases figure of merit and energy loss, while preserving the SONO structure that facilitates manufacturing
Solution Approach 2:
The patent creates local structural differentiation where the trench region has no dimple structure (improving efficiency) while the field region maintains the SONO structure (maintaining ease of manufacture), optimizing energy efficiency locally without sacrificing overall manufacturability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces total gate charge and FOM, improving switching speed and efficiency by forming a complete ONO structure and filling the gate oxide layer into the concave surface, thereby addressing the shortcomings of the dimple structure.
Implementation Method 1
forming a first oxide layer over the epitaxial layer, the sidewall and the bottom, and then forming a first nitride layer over the first oxide layer
Implementation Method 2
forming a first oxide layer over the epitaxial layer, the sidewall and the bottom, and then forming a first nitride layer over the first oxide layer
Data Source
AI summary
A field effect transistor includes a substrate, an epitaxial layer, a remnant-oxide layer, an electrode, a surrounding-oxide layer, a surrounding-nitride layer, a gate oxide layer, a gate, a P-body region, a source region, an interlayer dielectric and a source electrode. The epitaxial layer on the substrate has a trench having a sidewall and a bottom. The electrode inside the trench is coated subsequently by the surrounding-oxide layer, the surrounding-nitride layer and the remnant-oxide layer. The gate formed on the gate oxide layer is separated from the electrode sequentially by the gate oxide layer, the surrounding-nitride layer and the surrounding-oxide layer. The P-body region and the source region, formed at the epitaxial layer, are separated from the gate by the gate oxide layer. The interlayer dielectric covers the source region and the gate. The source electrode covers the P-body region and the interlayer dielectric, and contacts the source region.