Power MOSFET Empty Space Zones Reduce Parasitic Capacitance
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Solution Overview
Problem
Power MOSFETs face challenges in minimizing specific on-resistance (RSP) and switching losses due to increased intrinsic capacitances as cell density increases, and existing techniques face limitations in trench filling and void formation during manufacturing.
Innovation Solution
Incorporating one or more insulated empty space zones near semiconductor regions, particularly in drift regions, to reduce parasitic capacitance and Miller charge, while introducing permanent charge at the interface between these zones and semiconductor regions, which helps in shaping off-state potential contours and on-state carrier densities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If cell density is increased to reduce specific on-resistance, then on-resistance decreases, but intrinsic capacitances increase causing switching power loss to increase
Solution Approach 1:
The patent extracts the harmful dielectric material from the trench bottom and replaces it with empty space, removing the source of parasitic capacitance. This allows high cell density to be maintained without the penalty of increased capacitance-induced switching losses.
Solution Approach 2:
The patent introduces a porous or hollow structure at the trench bottom (empty space zone), creating a configuration that occupies volume without adding dielectric material. This reduces the parasitic capacitance while maintaining the electrical field control function.
2Loss of energy
If trench width is narrowed to reduce gate-to-drain capacitance, then gate-to-drain capacitance decreases, but trench filling becomes incomplete creating voids
Solution Approach 1:
The patent deliberately removes dielectric material from the trench bottom to create an empty space zone, transforming the harmful effect of incomplete filling into a beneficial feature that reduces parasitic capacitance while ensuring complete and reliable trench filling.
Solution Approach 2:
The patent converts the manufacturing challenge of incomplete trench filling into a beneficial empty space zone that reduces parasitic capacitance. What was previously a defect (voids) becomes a deliberate design feature that improves device performance.
3Reliability
If BOX thickness is increased to decouple gate from drain, then gate decoupling improves, but trench filling becomes more difficult
Solution Approach 1:
The patent removes dielectric material from the trench bottom to create an empty space zone, eliminating the need for thick BOX while achieving superior gate decoupling. This simplifies manufacturing by allowing complete trench filling without the complexity of depositing and managing thick oxide layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces parasitic capacitance, Miller charge, and switching losses, while simplifying the fabrication process by allowing for a narrower trench width and deeper trench depth, enabling more efficient power device performance.
Implementation Method 1
the empty space zone 180...provides reduced parasitic capacitance
Implementation Method 2
introducing permanent charge at the interface between these zones and semiconductor regions, which helps in shaping off-state potential contours and on-state carrier densities
Data Source
AI summary
Power semiconductor devices in which insulated empty space zones are used for field-shaping regions, in place of dielectric bodies previously used. Optionally permanent charge is added at the interface between the insulated empty space zone and an adjacent semiconductor drift region.