MOSFET ESD Resistance via Localized Drift Region Doping
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Solution Overview
Problem
High breakdown voltage ICs face challenges in enhancing Electrostatic Discharge (ESD) resistance, particularly in n-type channel MOSFETs with triple well structures, leading to increased chip size and cost due to the need for extensive ESD protection diodes, and existing solutions like adaptive resurf and thyristor structures complicate the manufacturing process and reduce punch-through breakdown voltage.
Innovation Solution
A semiconductor device with a second conductivity type well layer and offset layers, where the diffusion depth of the high concentration layer is less than under the LOCOS oxide film, and a thicker second n-type offset layer is formed to prevent depletion layer reach and electrical field concentration, thereby increasing ESD resistance without increasing chip size or process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an ESD protection diode with large area is provided in the abnormal current detection output terminal, then ESD resistance is improved, but chip size increases
Solution Approach 1:
The patent applies local quality by creating a high concentration n-type layer specifically in the drift region beneath the drain, while other regions maintain their original doping concentrations. This localized modification enhances ESD resistance precisely where needed without requiring a large area protection diode, thus resolving the contradiction between reliability and chip size.
Solution Approach 2:
The patent changes the doping concentration parameter by forming a high concentration n-type layer with impurity concentration higher than the surrounding offset layer. This parameter change increases the ESD resistance of the MOSFET itself, eliminating the need for additional large-area protection elements and reducing overall chip size.
2Reliability
If adaptive resurf or thyristor structure is added to increase ESD resistance, then ESD resistance is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the ESD protection function directly into the existing MOSFET structure by modifying the drift region doping, rather than adding separate protection circuits like adaptive resurf or thyristor structures. This integration simplifies the manufacturing process while achieving improved ESD resistance.
3Reliability
If adaptive resurf or thyristor structure is added to increase ESD resistance, then ESD resistance is improved, but punch-through breakdown voltage decreases
Solution Approach 1:
The patent applies local quality by restricting the high concentration n-type layer formation to specific regions of the drift zone beneath the drain, while maintaining lower doping concentrations in other areas. This selective doping enhancement improves ESD resistance without creating the widespread structural modifications that would compromise punch-through breakdown voltage.
Solution Approach 2:
The patent uses partial action by applying high concentration doping only to the necessary portion of the drift region rather than throughout the entire structure. This targeted approach provides sufficient ESD protection while preserving the electrical characteristics needed for maintaining punch-through breakdown voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances ESD resistance by preventing depletion layer reach and electrical field concentration, reducing thermal destruction and localized current concentration, while maintaining or improving breakdown voltage without the need for additional protective elements or complex processes, thus reducing chip size and cost.
Implementation Method 1
the diffusion depth of the second well layer below the high concentration layer is less than the diffusion depth of the second well layer below the LOCOS oxide film
Data Source
AI summary
A semiconductor device and manufacturing method are disclosed which provide increased ESD resistance. By disposing a slit mask when forming a second p-type well layer, impurity concentration of the second p-type well layer is partially reduced. By forming a second n-type offset layer in the second p-type well layer having decreased impurity concentration, it is possible to increase thickness of the second n-type offset layer in this place compared with that heretofore known. By increasing thickness of the second n-type offset layer, a depletion layer does not reach an n-type drain layer at a low voltage when reverse bias is applied to the drain. It thus is possible to prevent thermal destruction caused by localized electrical field concentration. As a result, it is possible to increase ESD resistance. As it is sufficient to replace a photoresist mask, there is no increase in the number of processes.