MOSFET ESD Protection Circuit With Dynamic Gate Voltage Control
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Solution Overview
Problem
As semiconductor devices become finer and reduce in power, the withstand voltage of elements like transistors decreases, necessitating improved ESD protection circuits that control gate voltage to prevent transistor breakdown while maintaining ESD protection capability.
Innovation Solution
An ESD protection circuit with a control circuit that outputs a first voltage to the gate of an n-channel MOS transistor during normal operation and a second, lower voltage during an ESD event, using an RC circuit to manage gate voltage and suppress transistor breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a low withstand voltage type transistor is used in an ESD protection circuit, then power consumption is reduced and device scaling is improved, but the transistor becomes susceptible to breakdown under ESD conditions
Solution Approach 1:
The gate voltage of the n-channel MOS transistor is dynamically adjusted based on operating conditions. During normal operation, a first voltage (Vdd - Vth) is applied to the gate to maintain low power consumption. During ESD events, a second voltage (Vdd - 2Vth) is applied to enhance the transistor's withstand capability. This dynamic voltage adjustment resolves the contradiction between low power operation and ESD protection capability.
Solution Approach 2:
The invention changes the gate voltage parameter of the n-channel MOS transistor depending on the operational state. By switching between two distinct voltage levels (Vdd - Vth for normal operation and Vdd - 2Vth for ESD protection), the transistor's electrical characteristics are optimized for different conditions, allowing low power consumption during normal operation while maintaining high reliability during ESD events.
2Reliability
If the gate voltage is increased to improve ESD protection capability, then transistor breakdown resistance is improved, but power consumption increases and device scaling is compromised
Solution Approach 1:
The gate voltage is dynamically controlled to be high (Vdd - 2Vth) only during ESD events when protection is needed, and low (Vdd - Vth) during normal operation when protection is not required. This temporal separation of high and low voltage states allows the system to achieve high ESD protection capability without incurring continuous high power consumption.
Solution Approach 2:
The control circuit periodically monitors for ESD conditions and adjusts the gate voltage accordingly. The RC circuit generates control signals that are applied to the transistor gate in response to detected ESD events, creating a periodic control mechanism that switches between protection and normal operation modes based on environmental conditions.
3Reliability
If a control circuit is added to dynamically adjust gate voltage, then both ESD protection capability and power efficiency are improved, but device complexity increases
Solution Approach 1:
An RC circuit is introduced as an intermediary element that automatically generates control signals for the transistor gate voltage adjustment. This passive RC network responds to ESD events by producing appropriate voltage levels without requiring complex active control logic, thereby achieving dynamic gate voltage control with minimal additional circuit complexity.
Solution Approach 2:
The RC circuit is configured to automatically detect ESD conditions and generate the appropriate control signals for gate voltage adjustment without external intervention. The circuit serves itself by using its own components (resistor and capacitor) to generate the timing and voltage control signals needed, eliminating the need for additional complex control logic or external control mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances ESD protection capability while preventing transistor breakdown, even with low withstand voltage transistors, by managing gate voltage effectively during normal and surge conditions.
Implementation Method 1
an RC circuit that generates a control voltage in response to an ESD event
Data Source
AI summary
A semiconductor device includes: an ESD protection circuit including a first n-channel MOS transistor provided between a signal terminal and a ground wire; and a control circuit electrically connected to the signal terminal, wherein, while a signal of a high level is being supplied to the signal terminal, the control circuit outputs a first voltage dropped from a high-level voltage of the signal to a gate of the first n-channel MOS transistor, and in response to a surge due to ESD being input into the signal terminal, outputs a second voltage lower than the first voltage to the gate of the first n-channel MOS transistor.