MOSFET Field Doping Layout for Compact Multi-Voltage Isolation
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Solution Overview
Problem
Existing high-voltage semiconductor devices face challenges in maintaining a small device size while achieving different application voltages without adding additional masks, particularly in ultra-high voltage (UHV) device process platforms.
Innovation Solution
A semiconductor device design incorporating a field doped region with varying doping depths and a gate structure that extends to cover isolation structures, formed using a local oxidation of silicon (LOCOS) process without additional masks, to adjust doping concentrations and maintain electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional masks are added to form MOSFET devices with different application voltages, then the voltage adaptability is improved, but the device complexity and manufacturing process complexity increase
Solution Approach 1:
The patent applies local quality by creating different doping concentrations and depths within the same field doped region. The field doped region has a first portion with a first doping concentration and depth, and a second portion with a second doping concentration and depth. This allows different voltage characteristics to be achieved in different areas of the same device structure, enabling multiple application voltages without additional masks while maintaining process simplicity
Solution Approach 2:
The patent utilizes parameter changes by varying the doping concentration and depth parameters within the field doped region. By controlling the ion implantation parameters (dose, energy, angle) to create different doping profiles in the first and second portions, the device can achieve different threshold voltages and operating characteristics, providing voltage adaptability through parameter optimization rather than structural complexity
2Area of moving object
If the device size is reduced, then the integration density is improved, but the withstand voltage capability deteriorates
Solution Approach 1:
The patent applies the nesting principle by placing the field doped region with varying depths within the well region, and the gate structure extending over both the well region and isolation structure. The multi-depth field doped region is nested within the single well region, allowing compact vertical integration that maintains small device footprint while achieving the necessary voltage blocking capability through the deeper first portion of the field doped region
Solution Approach 2:
The patent transitions from two-dimensional planar scaling to three-dimensional vertical structuring. By creating a field doped region with different depths (first portion deeper than second portion) within the same lateral footprint, and having the gate structure extend vertically over the isolation structure, the design achieves voltage handling capability through vertical dimension optimization rather than lateral scaling, maintaining small device size while ensuring reliability
3Manufacturing precision
If a single well region is used without additional masks, then the manufacturing precision is improved, but the ability to achieve different application voltages deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the field doped region into a first portion and a second portion with different doping concentrations and depths, both formed within the same well region using a single mask. This segmentation of the doping profile (rather than the device structure or mask set) enables different voltage characteristics to be achieved through selective ion implantation parameters, maintaining manufacturing precision while providing application voltage versatility
Solution Approach 2:
The patent achieves universality by designing a single well region structure that can serve multiple voltage application purposes. The field doped region with its first and second portions acts as a multi-functional element that can be optimized for different voltage requirements through parameter adjustment rather than structural modification, allowing the same basic device architecture to be adapted for different application voltages without additional masks
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for the production of MOSFET devices with low operation voltage within 20V, maintaining a small size and achieving desired electrical properties and withstand voltage requirements.
Implementation Method 1
a field doped region having a second conductivity type is disposed on the well region, wherein the field doped region has a first portion overlapping the isolation structure and a second portion connected to the first portion and disposed away from the gate structure
Implementation Method 2
The gate structure includes a gate dielectric layer and is disposed on the semiconductor substrate in the well region
Implementation Method 3
The isolation structure is disposed on the semiconductor substrate in the well region
Data Source
AI summary
A semiconductor device and a method for forming the same are provided. The semiconductor device includes a semiconductor substrate, a well region, an isolation structure, a gate structure and a field doped region. The well region having a first conductivity type is disposed in the semiconductor substrate. The gate structure extends to cover a portion of the isolation structure in the well region. The field doped region having a second conductivity type is disposed on the well region. The field doped region has a first portion overlapping the isolation structure and a second portion that is connected to the first portion and away from the gate structure. A first depth between a bottom surface of the first portion and a top surface of the semiconductor structure is greater than a second depth between a bottom surface of the second portion and the top surface of the semiconductor structure.