High-Voltage MOSFET Field Plate Gate Structure
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Solution Overview
Problem
Current high-voltage MOSFETs require increased breakdown voltage to meet evolving semiconductor device performance requirements, and existing designs do not effectively achieve this without compromising electric field uniformity and silicide formation.
Innovation Solution
The semiconductor device incorporates a field plate gate structure and a dummy gate structure to extend the lateral distance between the source and drain regions, using a resist-protection-oxide pattern and conductive layers to create a combined gate structure that is electrically coupled to the gate voltage, while the dummy gate prevents silicide formation and allows the field plate gate to be pulled away from the drain, resulting in a more uniform electric field and higher breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the lateral distance between source and drain regions is increased to achieve higher breakdown voltage, then the breakdown voltage is improved, but the device area increases and manufacturing complexity increases
Solution Approach 1:
The patent introduces a vertical field plate gate structure that extends over the drain region, adding a vertical dimension to the gate structure. This allows the electric field to be controlled in the vertical direction rather than requiring increased lateral distance, thereby maintaining compact device area while achieving higher breakdown voltage through enhanced vertical electric field management.
Solution Approach 2:
The gate structure is segmented into a conventional gate region and an extended field plate gate region. The field plate gate is separated from the main gate and positioned to specifically control the electric field near the drain, allowing independent optimization of different regions for different functions (current control vs. breakdown voltage enhancement).
2Reliability
If the field plate gate is positioned closer to the drain to enhance electric field control, then the breakdown voltage is improved, but silicide formation occurs between the gate and drain regions
Solution Approach 1:
The harmful silicide formation issue is resolved by extracting or removing the field plate gate from direct contact with the drain region. The field plate gate is positioned to overlap the drain region vertically but is electrically isolated, allowing it to control the electric field without forming silicides with the drain, thus eliminating the harmful effect while maintaining the beneficial breakdown voltage enhancement.
Solution Approach 2:
An insulating layer or spacer is introduced as an intermediary between the field plate gate and the drain region. This intermediary prevents direct contact and silicide formation while still allowing the field plate gate to exert electric field control over the drain region through the insulating barrier, thus resolving the contradiction between close positioning and silicide prevention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves a higher breakdown voltage and more uniform electric field in the channel region, enabling the semiconductor device to operate at higher voltages with improved performance and preventing undesired silicide formation.
Implementation Method 1
This configuration achieves a higher breakdown voltage and more uniform electric field in the channel region
Implementation Method 2
using a resist-protection-oxide pattern and conductive layers to create a combined gate structure that is electrically coupled to the gate voltage
Implementation Method 3
the dummy gate prevents silicide formation and allows the field plate gate to be pulled away from the drain
Data Source
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AI summary
A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in a portion of the semiconductor substrate. The first well doped region has a second conductivity type. A first doped region is formed on the first well doped region, having the second conductivity type. A second doped region is formed on the first well doped region and is separated from the first doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and is adjacent to the first doped region. A second gate structure is formed beside the first gate structure and is close to the second doped region. A third gate structure is formed overlapping a portion of the first gate structure and a first portion of the second gate structure.