Multi-Gate MOSFET Fin Height Control via Epitaxial Growth
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Solution Overview
Problem
Conventional multi-gate non-planar MOSFET manufacturing processes face challenges such as punch-through ion implantation causing Vt variation and fin height variations due to reactive ion etching, leading to non-uniform device characteristics and potential short circuits.
Innovation Solution
The proposed multi-gate metal oxide silicon transistor eliminates the need for punch-through ion implantation and uses an epitaxial process to define fin height, featuring a bulk silicon substrate with convex portions, dielectric layers, and laterally grown silicon portions to reduce source/drain resistance and prevent short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If punch-through ion implantation is used to prevent short circuits, then device reliability is improved, but threshold voltage variation increases
Solution Approach 1:
The patent removes the punch-through ion implantation step from the manufacturing process entirely. Instead of using ion implantation to prevent short circuits, the invention uses a different structural approach with selective epitaxial growth and spacer formation that achieves short circuit prevention without the harmful side effect of threshold voltage variation.
Solution Approach 2:
The patent changes the manufacturing approach from ion implantation (which alters electrical parameters) to selective epitaxial growth and physical spacer formation. This parameter change allows short circuit prevention through structural design rather than electrical parameter modification, thereby maintaining threshold voltage uniformity.
2Shape
If reactive ion etching is used to form fins, then fin structure is created, but fin height variation increases
Solution Approach 1:
The patent replaces the reactive ion etching process (mechanical/chemical removal) with selective epitaxial growth (controlled material deposition). This substitution allows for more precise control of fin height and reduced variation because epitaxial growth can be better controlled through temperature and time parameters compared to etching processes.
Solution Approach 2:
The selective epitaxial growth process inherently provides self-limiting behavior where the fin height is determined by the growth conditions and substrate properties rather than requiring precise etch depth control. This self-service characteristic reduces fin height variation without additional process steps.
3Reliability
If conventional multi-gate MOSFET manufacturing is used, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent extracts and removes several complex process steps from conventional multi-gate MOSFET manufacturing, including punch-through ion implantation and complex fin formation processes. By eliminating these steps while maintaining device performance through alternative structural approaches, the manufacturing complexity is reduced.
Solution Approach 2:
The patent applies local quality by forming fins only in specific regions where they are needed for device performance, rather than uniformly across the entire substrate. This selective formation approach simplifies the overall manufacturing process by reducing the number of structures that require precise control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in substantially uniform device characteristics, reduced fin height variations, cost-effective bulk silicon substrate usage, and prevention of short circuits between the fin and silicon substrate.
Implementation Method 1
forming a silicon germanium layer over a bulk silicon substrate, and forming a silicon layer over the silicon germanium layer
Data Source
AI summary
Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench regions; one or more dielectric portions over the convex portions; one or more silicon fins over the dielectric portions; a shallow trench isolation layer in the shallow trench isolation regions; and a gate electrode. The upper surface of the shallow trench isolation layer can be located below the upper surface of the convex portion, or the upper surface of the shallow trench isolation layer can be located between the lower surface and the upper surface of first dielectric layer. The multi-gate metal oxide silicon transistor can contain second spacers adjacent to side surfaces of the convex portions in a source/drain region.