MOSFET Fin Channel Partition Layout for Electrical Isolation
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Solution Overview
Problem
The reduction in size of metal oxide semiconductor field effect transistors (MOSFETs) in semiconductor devices deteriorates their operating characteristics and reliability due to high integration, necessitating improved electrical performance and manufacturing methods.
Innovation Solution
A semiconductor device design featuring first and second active fins with channel patterns and gate electrodes, where a lower partition with varying widths in different directions enhances electrical connectivity and reliability, including a first portion with a greater width on the upper surface and a second portion with a lesser width on the lower surface, extending continuously along the active fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of MOSFETs is reduced to increase integration density, then the quantity of devices per unit area increases, but the operating characteristics and reliability deteriorate
Solution Approach 1:
The lower partition extends in the third direction (vertical direction perpendicular to the substrate) from the space between channel patterns to the space between active fins. This vertical extension provides electrical isolation between adjacent MOSFETs without requiring increased lateral spacing, thus maintaining high integration density while ensuring reliable operation through proper channel separation.
Solution Approach 2:
The lower partition acts as an intermediary structure between adjacent channel patterns and active fins. It provides the necessary electrical isolation and structural separation to prevent interference between neighboring MOSFETs, enabling high-density integration while maintaining individual device reliability and operating characteristics.
2Reliability
If the width of the lower partition is increased to improve electrical isolation, then the reliability improves, but the channel width available for current flow decreases
Solution Approach 1:
The lower partition utilizes the vertical dimension (third direction) to provide electrical isolation rather than increasing its width in the lateral direction. This allows the partition to effectively separate adjacent channels vertically while minimizing its lateral footprint, thus maintaining maximum channel width for current flow while ensuring proper electrical isolation for reliability.
Data Source
AI summary
A semiconductor device includes a first channel pattern on a first active fin, a second channel pattern on a second active fin, a lower partition located between the first channel pattern and the second channel pattern, wherein the lower partition includes a first portion extending in a vertical direction from a space between the first channel pattern and the second channel pattern to a space between the first active fin and the second active fin and a second portion on the first portion, wherein a width of the first portion in a second horizontal direction on an upper surface of the first portion is greater than a width of the second portion in the second horizontal direction on a lower surface of the second portion, and the first portion extends continuously in a first horizontal direction along the first active fin and the second active fin.