Trench Power MOSFET Self-Aligned Gate Depth Control
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Solution Overview
Problem
Conventional split-gate trench power MOSFETs face challenges in controlling the depth of the main gate, leading to large process windows, increased gate-to-drain overlap, and significant variation in gate-to-drain capacitance, which degrades the performance and consistency of power MOSFETs.
Innovation Solution
The method involves forming a trench power MOSFET with a self-aligned N-type Doped Drain (NDD) region and a conductive field plate, where the main gate overlaps the NDD region, with a dielectric layer separating the main gate and field plate, and p-bodies formed at specific levels to reduce process variations and minimize gate-to-drain capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the depth of the trench and thickness of the dielectric layer are increased to ensure the epitaxy region is at the same level as the main gate, then the channel control is improved, but the gate-to-drain overlap increases and gate-to-drain capacitance variation increases
Solution Approach 1:
The patent forms the N-type Doped Drain region and field plate structure before forming the main gate, establishing a self-aligned configuration that pre-determines the gate-to-drain overlap region. This preliminary structuring ensures consistent alignment without requiring precise control of trench depth and dielectric thickness, thereby reducing capacitance variation while maintaining channel control.
2Ease of manufacture
If a large process window is used to ensure the epitaxy region is at the same level as the main gate, then manufacturing flexibility is improved, but gate-to-drain overlap and capacitance variation increase
Solution Approach 1:
The patent employs a self-aligned fabrication approach where the N-type Doped Drain region and field plate automatically define the position of the main gate through subsequent processing steps. This self-alignment mechanism eliminates the need for large process windows to ensure proper positioning, achieving both ease of manufacture and precise gate-to-drain overlap control simultaneously.
3Reliability
If the main gate depth is increased to control the entire channel, then channel control is improved, but the gate-to-drain capacitance increases
Solution Approach 1:
The patent divides the gate structure into two functional segments: the main gate for channel control and the field plate for electric field management. The field plate extends into the trench and overlaps with the N-type Doped Drain region, allowing the main gate to be positioned optimally for channel control while the field plate manages the electric field to minimize gate-to-drain capacitance. This segmentation enables independent optimization of both channel control and capacitance reduction.
Data Source
AI summary
A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.