MOSFET Gate Electrode Formation via Dummy Gate Template
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in efficiently forming high-quality gate electrode layers for MOSFET devices, particularly in maintaining a high wafers per hour output rate without compromising the quality of the gate electrode layer, especially when dealing with varying channel lengths of MOSFET devices.
Innovation Solution
A method involving the formation of a dummy gate stack, followed by the creation of source/drain regions, spacers, and subsequent removal of the dummy gate stack to form an opening for a gate dielectric layer and work function metal layer, which is then filled with conductive materials using dual fill techniques to achieve a robust gate electrode layer, allowing for both short and long channel MOSFET devices to be fabricated with optimal quality and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional gate electrode layer formation methods are used, then the process is simple and fast, but the quality of the gate electrode layer deteriorates for MOSFET devices with varying channel lengths
Solution Approach 1:
A dummy gate stack is formed in advance before the actual gate electrode layer formation. This preliminary structure serves as a template that ensures proper alignment and positioning for subsequent gate electrode deposition, thereby guaranteeing high quality gate electrode layers for MOSFET devices with varying channel lengths while maintaining production efficiency
Solution Approach 2:
The dummy gate stack acts as an intermediary structure that facilitates the formation of high-quality gate electrode layers. It provides a reference framework during fabrication that ensures precise positioning and uniformity, particularly for devices with different channel lengths, without significantly impacting the overall production throughput
2Manufacturing precision
If different fabrication processes are used for short and long channel MOSFETs, then the quality of gate electrode layers is optimized for each type, but the manufacturing complexity increases
Solution Approach 1:
The dummy gate stack structure serves as a universal template that works for both short channel and long channel MOSFET devices. By using this common preliminary structure, the fabrication process can produce high-quality gate electrode layers for different device types without requiring separate specialized processes, thereby reducing manufacturing complexity while maintaining quality
Solution Approach 2:
The dummy gate stack enables local optimization of gate electrode layer quality for different channel lengths. The structure allows the fabrication process to accommodate varying device requirements within a single unified process flow, ensuring each region receives appropriate treatment for its specific channel length without increasing overall process complexity
Data Source
AI summary
A semiconductor device, and a method of fabrication, is introduced. In an embodiment, a dummy gate stack is formed on a substrate. Lightly-doped source/drain regions and highly-doped source/drain regions are formed in the substrate on either sides of the dummy gate stack. An inter-layer dielectric (ILD) layer is formed over the substrate. Subsequently, the dummy gate stack is removed and a gate stack is formed in an opening in the ILD layer. The gate stack is formed by forming an interfacial layer in the opening of the ILD layer, forming a gate dielectric layer over the interfacial layer, forming a work function metal layer over the gate dielectric layer, and forming one or more gate electrode layers over the work function metal layer. Contacts are formed in the ILD layer and one or more metallization layers are formed over the ILD layer.