MOSFET Gate Effective Width and Length Conjecture
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Solution Overview
Problem
Current methods for determining the effective width and length of a gate in MOSFETs are unreliable due to limited sampling and inability to reflect electrical properties, with existing techniques only measuring physical dimensions rather than those affecting performance.
Innovation Solution
A method to calculate the effective width and length of a design gate by evaluating optimal width and length errors using intrinsic gate channel capacitance and edge capacitance, iteratively minimizing deviations to optimize errors and determine the effective gate dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If TEM is used to measure gate dimensions, then physical width and length can be obtained, but the effective gate width and length related to electrical properties cannot be determined
Solution Approach 1:
The patent introduces capacitance measurement as an intermediary method to indirectly determine effective gate dimensions. By measuring the capacitance of the gate structure and using it as a mediator, the effective width and length can be calculated without directly observing them through TEM, thus resolving the information loss about electrical properties
Solution Approach 2:
The patent replaces the mechanical/physical measurement system (TEM imaging) with an electrical measurement system (capacitance measurement). This substitution allows the determination of effective dimensions that are relevant to electrical performance rather than just physical geometry
2Loss of time
If limited sampling is used in TEM, then measurement time is reduced, but reliability of results deteriorates
Solution Approach 1:
The patent enables the measurement system to self-correct and self-optimize by iteratively adjusting the effective width and length values until the calculated capacitance matches the measured capacitance. This self-service mechanism eliminates the need for extensive manual sampling while ensuring high reliability through mathematical optimization
3Measurement precision
If iterative optimization is performed to minimize width and length errors, then effective gate dimensions are accurately determined, but calculation complexity increases
Solution Approach 1:
The patent applies partial action by focusing the iterative optimization only on the width and length parameters that most significantly affect capacitance, rather than optimizing all possible parameters. This selective approach achieves sufficient accuracy without excessive calculation complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for accurate determination of effective gate dimensions, crucial for MOSFET performance, by iteratively optimizing errors and converging to reliable effective width and length values, enhancing process development and electrical properties.
Implementation Method 1
an intrinsic gate channel capacitance and an edge capacitance of a design gate by calculation... through measuring a measured inversion capacitance of the design gate group under an inversion voltage... through measuring a zero capacitance of the design gate group under a zero gate voltage
Data Source
AI summary
A method for conjecturing the effective size, i.e. the effective width or effective length, of a gate is disclosed. First, a first design gate group including a first gate design width and a first gate design length is provided. Second, an intrinsic gate channel capacitance and an edge capacitance of the first design gate are respectively obtained by calculation. Then a size error, i.e. a width error or a length error is predicted by means of the intrinsic gate channel capacitance and of the edge capacitance to calculate a calculated inversion capacitance and a predicted size deviation. Later, the size error is repeatedly predicted to minimize the predicted size deviation and to optimize the size error to obtain an optimized size error. Afterwards, the effective size of the gate are conjectured by means of the optimized size error.