MOSFET Gate Extension Layout for Leakage and Scaling Control
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Solution Overview
Problem
As semiconductor devices are scaled down, their operation characteristics deteriorate, leading to challenges in integration and performance improvement.
Innovation Solution
The semiconductor device incorporates specific impurity patterns and gate structures with extension regions and semiconductor layers to enhance electrical characteristics and integration, including different conductive impurities and semiconductor materials to control leakage current and improve current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If metal-oxide-semiconductor field effect transistors are scaled down to achieve higher integration, then device density increases, but operation characteristics deteriorate
Solution Approach 1:
The gate pattern is designed with different widths at different locations: a first width in the channel region and a second width in the extension region, where the second width is greater than the first width. This local variation in gate dimensions allows optimization of electrical characteristics in different regions, improving device operation while maintaining high integration density
Solution Approach 2:
The gate structure extends in both the first direction (parallel to substrate surface) and the second direction (crossing the first direction), creating a two-dimensional gate pattern. This dimensional extension increases the effective gate control area without increasing the footprint in the channel direction, thereby improving device performance while maintaining high integration
2Productivity
If device size is reduced to improve integration, then more devices fit on substrate, but leakage current increases
Solution Approach 1:
The gate pattern is formed to include extension regions before the main channel region, with the extension region having a larger width. This preliminary structural configuration provides enhanced control over the channel formation and reduces leakage current pathways before the active channel operates
Solution Approach 2:
Different regions of the gate pattern have different widths optimized for different functions: the extension region has a larger width to control leakage, while the channel region has a smaller width for high-density integration. This local differentiation addresses leakage without sacrificing integration density
Data Source
AI summary
A semiconductor device may include a first impurity pattern and a second impurity pattern spaced apart from each other in a first direction on a substrate, where the first direction may be parallel to an upper surface of the substrate and where the first and second impurity patterns may include impurities having different conductive types; a first semiconductor pattern between the first impurity pattern and the second impurity pattern; and a first gate pattern crossing the first semiconductor pattern. The first gate pattern may include a gate region and an extension region. The gate region may extend in a second direction, which may cross the first direction. The extension region may extend from the gate region in the first direction.