Gate Electrode Height Loss Reduction in MOSFET Manufacturing
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Solution Overview
Problem
Conventional MOSFET manufacturing processes experience significant height loss of the gate electrode due to the CMP and etching processes, leading to inconsistent device heights and manufacturing challenges.
Innovation Solution
A semiconductor device manufacturing method that reduces interlayer dielectric layer loss by conducting an ion implantation process with silicon or carbon ions, forming a loss reduction region, and subsequently forming a gate structure with a high-K dielectric layer and gate electrode, allowing for a lower pseudo gate electrode and higher gate electrode than conventional methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP and etching processes are used to form the gate electrode, then the gate structure can be formed, but significant height loss occurs leading to inconsistent device heights
Solution Approach 1:
The patent applies preliminary action by forming a protective layer on the interlayer dielectric layer before the CMP and etching processes. This protective layer prevents excessive loss of the interlayer dielectric layer during subsequent manufacturing steps, thereby maintaining consistent gate electrode height across devices.
Solution Approach 2:
The patent changes the physical and chemical parameters of the interlayer dielectric layer by modifying its composition or properties to reduce loss during CMP and etching. This parameter change allows the layer to better withstand the manufacturing processes while maintaining the required height precision.
2Manufacturing precision
If a large pseudo gate electrode height H1 is used, then the gate electrode height loss can be compensated, but the structure may block ion implantation or cause peeling
Solution Approach 1:
The patent performs preliminary actions by forming the protective layer and optimizing the pseudo gate electrode structure before ion implantation. This allows ion implantation to proceed effectively without being blocked by an excessively large pseudo gate electrode, while still achieving the required final gate electrode height after CMP and etching.
Solution Approach 2:
The patent applies local quality by creating a protective layer specifically on the interlayer dielectric layer where it is most needed during CMP and etching. This localized protection enables the use of a more moderate pseudo gate electrode height that doesn't block ion implantation, while still achieving the required height compensation after processing.
3Ease of manufacture
If a small pseudo gate electrode height H1 is used, then ion implantation is not blocked, but the final gate electrode height H2 becomes too small causing homogeneous issues
Solution Approach 1:
The patent changes the parameters of the interlayer dielectric layer by adding a protective layer with different erosion resistance properties. This allows the system to use a smaller pseudo gate electrode height H1 that doesn't block ion implantation, while the protective layer compensates for the reduced height by minimizing loss during CMP and etching, maintaining consistent final height H2.
Solution Approach 2:
The protective layer acts as an intermediary between the pseudo gate electrode and the CMP/etching processes. It enables the use of a moderate pseudo gate electrode height by mediating the interaction with subsequent processes, preventing both the blocking issue and the height loss issue simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the height loss of the gate electrode, providing more manufacturing margin and improving production yield by maintaining a consistent device height and reducing the need for large pseudo gate electrodes.
Implementation Method 1
forming a loss reduction region in the interlayer dielectric layer by conducting an ion implantation process comprising silicon ion or carbon ion on the semiconductor structure
Data Source
AI summary
A semiconductor device and its manufacturing method are presented. The manufacturing method includes providing a semiconductor structure comprising a substrate, at least one source region on the substrate, an interlayer dielectric layer covering a portion of the source region and having a cavity on the source region, and a pseudo gate insulation layer at the bottom of the cavity covering a portion of the source region; forming a barrier layer in the cavity; forming a loss reduction region in the interlayer dielectric layer by conducting an ion implantation process comprising silicon ion or carbon ion; removing the barrier layer; removing the pseudo gate insulation layer to expose a portion of the source region; and forming a gate structure on the exposed portion of the source region. This inventive concept reduces the loss of the interlayer dielectric layer, thus reduces the height loss of the gate electrode.